Abstract: This paper provides an in-depth study of Wireless
Sensor Network (WSN) application to monitor and control the
swiftlet habitat. A set of system design is designed and developed
that includes the hardware design of the nodes, Graphical User
Interface (GUI) software, sensor network, and interconnectivity for
remote data access and management. System architecture is proposed
to address the requirements for habitat monitoring. Such applicationdriven
design provides and identify important areas of further work
in data sampling, communications and networking. For this
monitoring system, a sensor node (MTS400), IRIS and Micaz radio
transceivers, and a USB interfaced gateway base station of Crossbow
(Xbow) Technology WSN are employed. The GUI of this monitoring
system is written using a Laboratory Virtual Instrumentation
Engineering Workbench (LabVIEW) along with Xbow Technology
drivers provided by National Instrument. As a result, this monitoring
system is capable of collecting data and presents it in both tables and
waveform charts for further analysis. This system is also able to send
notification message by email provided Internet connectivity is
available whenever changes on habitat at remote sites (swiftlet farms)
occur. Other functions that have been implemented in this system
are the database system for record and management purposes; remote
access through the internet using LogMeIn software. Finally, this
research draws a conclusion that a WSN for monitoring swiftlet
habitat can be effectively used to monitor and manage swiftlet
farming industry in Sarawak.
Abstract: In this paper, we proposed an efficient data
compression strategy exploiting the multi-resolution characteristic of
the wavelet transform. We have developed a sensor node called
“Smart Sensor Node; SSN". The main goals of the SSN design are
lightweight, minimal power consumption, modular design and robust
circuitry. The SSN is made up of four basic components which are a
sensing unit, a processing unit, a transceiver unit and a power unit.
FiOStd evaluation board is chosen as the main controller of the SSN
for its low costs and high performance. The software coding of the
implementation was done using Simulink model and MATLAB
programming language. The experimental results show that the
proposed data compression technique yields recover signal with good
quality. This technique can be applied to compress the collected data
to reduce the data communication as well as the energy consumption
of the sensor and so the lifetime of sensor node can be extended.
Abstract: This paper describes a low-voltage and low-power
channel selection analog front end with continuous-time low pass
filters and highly linear programmable gain amplifier (PGA). The
filters were realized as balanced Gm-C biquadratic filters to achieve a
low current consumption. High linearity and a constant wide
bandwidth are achieved by using a new transconductance (Gm) cell.
The PGA has a voltage gain varying from 0 to 65dB, while
maintaining a constant bandwidth. A filter tuning circuit that requires
an accurate time base but no external components is presented.
With a 1-Vrms differential input and output, the filter achieves
-85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA
were implemented in a 0.18um 1P6M n-well CMOS process. They
consume 3.2mW from a 1.8V power supply and occupy an area of
0.19mm2.
Abstract: In this paper we propose a new criterion for solving
the problem of channel shortening in multi-carrier systems. In a
discrete multitone receiver, a time-domain equalizer (TEQ) reduces
intersymbol interference (ISI) by shortening the effective duration of
the channel impulse response. Minimum mean square error (MMSE)
method for TEQ does not give satisfactory results. In [1] a new
criterion for partially equalizing severe ISI channels to reduce the
cyclic prefix overhead of the discrete multitone transceiver (DMT),
assuming a fixed transmission bandwidth, is introduced. Due to
specific constrained (unit morm constraint on the target impulse
response (TIR)) in their method, the freedom to choose optimum
vector (TIR) is reduced. Better results can be obtained by avoiding
the unit norm constraint on the target impulse response (TIR). In
this paper we change the cost function proposed in [1] to the cost
function of determining the maximum of a determinant subject to
linear matrix inequality (LMI) and quadratic constraint and solve the
resulting optimization problem. Usefulness of the proposed method
is shown with the help of simulations.
Abstract: This paper presents a simple and original method for
the generation of short monocycle pulses based on the transient
response of a passive band-pass filter. The recorded sub-nanosecond
pulses show a good symmetry and a small ringing (13 % of the peak
amplitude). Their spectral density covers the range 3.1 GHz to
10.6 GHz. The possibility to adapt the pulse spectral density to the
indoor FCC frequency mask is demonstrated with a prototype
working at a reduced frequency (FCC/1000). A detection technique is
proposed.
Abstract: A design flow of multi-standard down-conversion
CMOS mixers for three modern standards: Global System Mobile,
Digital Enhanced Cordless Telephone and Universal Mobile
Telecommunication Systems is presented. Three active mixer-s
structures are studied. The first is based on the Gilbert cell which
gives a tolerable noise figure and linearity with a low conversion
gain. The second and third structures use the current bleeding and
charge injection techniques in order to increase the conversion gain.
An improvement of about 2 dB of the conversion gain is achieved
without a considerable degradation of the other characteristics. The
models used for noise figure, conversion gain and IIP3 used are
studied. This study describes the nature of trade-offs inherent in such
structures and gives insights that help in identifying which structure
is better for given conditions.
Abstract: A new digital transceiver circuit for asynchronous frame detection is proposed where both the transmitter and receiver contain all digital components, thereby avoiding possible use of conventional devices like monostable multivibrators with unstable external components such as resistances and capacitances. The proposed receiver circuit, in particular, uses a combinational logic block yielding an output which changes its state as soon as the start bit of a new frame is detected. This, in turn, helps in generating an efficient receiver sampling clock. A data latching circuit is also used in the receiver to latch the recovered data bits in any new frame. The proposed receiver structure is also extended from 4- bit information to any general n data bits within a frame with a common expression for the output of the combinational logic block. Performance of the proposed hardware design is evaluated in terms of time delay, reliability and robustness in comparison with the standard schemes using monostable multivibrators. It is observed from hardware implementation that the proposed circuit achieves almost 33 percent speed up over any conventional circuit.