Abstract: The end panels of a large rectangular industrial duct,
which experience significant internal pressures, also experience
considerable transverse shear due to transfer of gravity loads to the
supports. The current design practice of such thin plate panels for
shear load is based on methods used for the design of plate girder
webs. The structural arrangements, the loadings and the resulting
behavior associated with the industrial duct end panels are, however,
significantly different from those of the web of a plate girder. The
large aspect ratio of the end panels gives rise to multiple bands of
tension fields, whereas the plate girder web design is based on one
tension field. In addition to shear, the industrial end panels are
subjected to internal pressure which in turn produces significant
membrane action. This paper reports a study which was undertaken
to review the current industrial analysis and design methods and to
propose a comprehensive method of designing industrial duct end
panels for shear resistance. In this investigation, a nonlinear finite element model was
developed to simulate the behavior of industrial duct end panel, along
with the associated edge stiffeners, subjected to transverse shear and
internal pressures. The model considered the geometric imperfections
and constitutive relations for steels. Six scale independent
dimensionless parameters that govern the behavior of such end panel
were identified and were then used in a parametric study. It was
concluded that the plate slenderness dominates the shear strength of
stockier end panels, and whereas, both the plate slenderness and the
aspect ratio influence the shear strength of slender end panels. Based
on these studies, this paper proposes design aids for estimating the
shear strength of rectangular duct end panels.
Abstract: Shifted polynomial basis (SPB) is a variation of
polynomial basis representation. SPB has potential for efficient
bit level and digi -level implementations of multiplication over
binary extension fields with subquadratic space complexity. For
efficient implementation of pairing computation with large finite
fields, this paper presents a new SPB multiplication algorithm based
on Karatsuba schemes, and used that to derive a novel scalable
multiplier architecture. Analytical results show that the proposed
multiplier provides a trade-off between space and time complexities.
Our proposed multiplier is modular, regular, and suitable for very
large scale integration (VLSI) implementations. It involves less
area complexity compared to the multipliers based on traditional
decomposition methods. It is therefore, more suitable for efficient
hardware implementation of pairing based cryptography and elliptic
curve cryptography (ECC) in constraint driven applications.
Abstract: Steel plate shear walls (SPSWs) in buildings are
known to be an effective means for resisting lateral forces. By using
un-stiffened walls and allowing them to buckle, their energy
absorption capacity will increase significantly due to the postbuckling
capacity. The post-buckling tension field action of SPSWs
can provide substantial strength, stiffness and ductility. This paper
presents the Finite Element Analysis of low yield point (LYP) steel
shear walls. In this shear wall system, the LYP steel plate is used for
the steel panel and conventional structural steel is used for boundary
frames. A series of nonlinear cyclic analyses were carried out to
obtain the stiffness, strength, deformation capacity, and energy
dissipation capacity of the LYP steel shear wall. The effect of widthto-
thickness ratio of steel plate on buckling behavior, and energy
dissipation capacities were studied. Good energy dissipation and
deformation capacities were obtained for all models.
Abstract: A new and highly efficient architecture for elliptic curve scalar point multiplication which is optimized for a binary field recommended by NIST and is well-suited for elliptic curve cryptographic (ECC) applications is presented. To achieve the maximum architectural and timing improvements we have reorganized and reordered the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. With G=41, the proposed design is capable of performing a field multiplication over the extension field with degree 163 in 11.92 s with the maximum achievable frequency of 251 MHz on Xilinx Virtex-4 (XC4VLX200) while 22% of the chip area is occupied, where G is the digit size of the underlying digit-serial finite field multiplier.