Abstract: Software development for complex systems requires
efficient and automatic tools that can be used to verify the
satisfiability of some critical properties such as security ones. With
the emergence of Aspect-Oriented Programming (AOP), considerable
work has been done in order to better modularize the separation of
concerns in the software design and implementation. The goal is to
prevent the cross-cutting concerns to be scattered across the multiple
modules of the program and tangled with other modules. One of the
key challenges in the aspect-oriented programs is to be sure that all
the pieces put together at the weaving time ensure the satisfiability
of the overall system requirements. Our paper focuses on this problem and proposes a formal property
verification approach for a given property from the woven program.
The approach is based on the control flow graph (CFG) of the
woven program, and the use of a satisfiability modulo theories (SMT)
solver to check whether each property (represented par one aspect)
is satisfied or not once the weaving is done.
Abstract: In this paper a Public Key Cryptosystem is proposed
using the number theoretic transforms (NTT) over a ring of integer
modulo a composite number. The key agreement is similar to
ElGamal public key algorithm. The security of the system is based on
solution of multivariate linear congruence equations and discrete
logarithm problem. In the proposed cryptosystem only fixed numbers
of multiplications are carried out (constant complexity) and hence the
encryption and decryption can be done easily. At the same time, it is
very difficult to attack the cryptosystem, since the cipher text is a
sequence of integers which are interrelated. The system provides
authentication also. Using Mathematica version 5.0 the proposed
algorithm is justified with a numerical example.
Abstract: Efficient modulo 2n+1 adders are important for
several applications including residue number system, digital signal
processors and cryptography algorithms. In this paper we present a
novel modulo 2n+1 addition algorithm for a recently represented
number system. The proposed approach is introduced for the
reduction of the power dissipated. In a conventional modulo 2n+1
adder, all operands have (n+1)-bit length. To avoid using (n+1)-bit
circuits, the diminished-1 and carry save diminished-1 number
systems can be effectively used in applications. In the paper, we also
derive two new architectures for designing modulo 2n+1 adder, based
on n-bit ripple-carry adder. The first architecture is a faster design
whereas the second one uses less hardware. In the proposed method,
the special treatment required for zero operands in Diminished-1
number system is removed. In the fastest modulo 2n+1 adders in
normal binary system, there are 3-operand adders. This problem is
also resolved in this paper. The proposed architectures are compared
with some efficient adders based on ripple-carry adder and highspeed
adder. It is shown that the hardware overhead and power
consumption will be reduced. As well as power reduction, in some
cases, power-delay product will be also reduced.
Abstract: SAD (Sum of Absolute Difference) algorithm is
heavily used in motion estimation which is computationally highly
demanding process in motion picture encoding. To enhance the
performance of motion picture encoding on a VLIW processor, an
efficient implementation of SAD algorithm on the VLIW processor is
essential. SAD algorithm is programmed as a nested loop with a
conditional branch. In VLIW processors, loop is usually optimized by
software pipelining, but researches on optimal scheduling of software
pipelining for nested loops, especially nested loops with conditional
branches are rare. In this paper, we propose an optimal scheduling and
implementation of SAD algorithm with conditional branch on a VLIW
DSP processor. The proposed optimal scheduling first transforms the
nested loop with conditional branch into a single loop with conditional
branch with consideration of full utilization of ILP capability of the
VLIW processor and realization of earlier escape from the loop. Next,
the proposed optimal scheduling applies a modulo scheduling
technique developed for single loop. Based on this optimal scheduling
strategy, optimal implementation of SAD algorithm on TMS320C67x,
a VLIW DSP is presented. Through experiments on TMS320C6713
DSK, it is shown that H.263 encoder with the proposed SAD
implementation performs better than other H.263 encoder with other
SAD implementations, and that the code size of the optimal SAD
implementation is small enough to be appropriate for embedded
environments.
Abstract: As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.
Abstract: In this work, we first give in what fields Fp, the cubic
root of unity lies in F*p, in Qp and in K*p where Qp and K*p denote
the sets of quadratic and non-zero cubic residues modulo p. Then we
use these to obtain some results on the classification of the Bachet
elliptic curves y2 ≡ x3 +a3 modulo p, for p ≡ 1 (mod 6) is prime.
Abstract: Let n ≥ 3 be an integer and p be a prime odd number. Let us consider Gp(n) the subgroup of (Z/nZ)* defined by : Gp(n) = {x ∈ (Z/nZ)* / xp = 1}. In this paper, we give an algorithm that computes a generating set of this subgroup.
Abstract: The purpose of this research is to study the concepts
of multiple Cartesian product, variety of multiple algebras and to
present some examples. In the theory of multiple algebras, like other
theories, deriving new things and concepts from the things and
concepts available in the context is important. For example, the first
were obtained from the quotient of a group modulo the equivalence
relation defined by a subgroup of it. Gratzer showed that every
multiple algebra can be obtained from the quotient of a universal
algebra modulo a given equivalence relation.
The purpose of this study is examination of multiple algebras and
basic relations defined on them as well as introduction to some
algebraic structures derived from multiple algebras. Among the
structures obtained from multiple algebras, this article studies submultiple
algebras, quotients of multiple algebras and the Cartesian
product of multiple algebras.
Abstract: Let n ≥ 3 be an integer and G2(n) be the subgroup
of square roots of 1 in (Z/nZ)*. In this paper, we give an algorithm
that computes a generating set of this subgroup.
Abstract: Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m2 . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.
Abstract: In this work, we consider the rational points on elliptic
curves over finite fields Fp. We give results concerning the number
of points Np,a on the elliptic curve y2 ≡ x3 +a3(mod p) according
to whether a and x are quadratic residues or non-residues. We use
two lemmas to prove the main results first of which gives the list of
primes for which -1 is a quadratic residue, and the second is a result
from [1]. We get the results in the case where p is a prime congruent
to 5 modulo 6, while when p is a prime congruent to 1 modulo 6,
there seems to be no regularity for Np,a.
Abstract: In this study, we examine multiple algebras and
algebraic structures derived from them and by stating a theory on
multiple algebras; we will show that the theory of multiple algebras
is a natural extension of the theory of universal algebras. Also, we
will treat equivalence relations on multiple algebras, for which the
quotient constructed modulo them is a universal algebra and will
study the basic relation and the fundamental algebra in question.
In this study, by stating the characteristic theorem of multiple
algebras, we show that the theory of multiple algebras is a natural
extension of the theory of universal algebras.
Abstract: Modular multiplication is the basic operation
in most public key cryptosystems, such as RSA, DSA, ECC,
and DH key exchange. Unfortunately, very large operands
(in order of 1024 or 2048 bits) must be used to provide
sufficient security strength. The use of such big numbers
dramatically slows down the whole cipher system, especially
when running on embedded processors.
So far, customized hardware accelerators - developed on
FPGAs or ASICs - were the best choice for accelerating
modular multiplication in embedded environments. On the
other hand, many algorithms have been developed to speed
up such operations. Examples are the Montgomery modular
multiplication and the interleaved modular multiplication
algorithms. Combining both customized hardware with
an efficient algorithm is expected to provide a much faster
cipher system.
This paper introduces an enhanced architecture for computing
the modular multiplication of two large numbers X
and Y modulo a given modulus M. The proposed design is
compared with three previous architectures depending on
carry save adders and look up tables. Look up tables should
be loaded with a set of pre-computed values. Our proposed
architecture uses the same carry save addition, but replaces
both look up tables and pre-computations with an enhanced
version of sign detection techniques. The proposed architecture
supports higher frequencies than other architectures.
It also has a better overall absolute time for a single operation.