Abstract: With the rapid development of deep learning, neural network and deep learning algorithms play a significant role in various practical applications. Due to the high accuracy and good performance, Convolutional Neural Networks (CNNs) especially have become a research hot spot in the past few years. However, the size of the networks becomes increasingly large scale due to the demands of the practical applications, which poses a significant challenge to construct a high-performance implementation of deep learning neural networks. Meanwhile, many of these application scenarios also have strict requirements on the performance and low-power consumption of hardware devices. Therefore, it is particularly critical to choose a moderate computing platform for hardware acceleration of CNNs. This article aimed to survey the recent advance in Field Programmable Gate Array (FPGA)-based acceleration of CNNs. Various designs and implementations of the accelerator based on FPGA under different devices and network models are overviewed, and the versions of Graphic Processing Units (GPUs), Application Specific Integrated Circuits (ASICs) and Digital Signal Processors (DSPs) are compared to present our own critical analysis and comments. Finally, we give a discussion on different perspectives of these acceleration and optimization methods on FPGA platforms to further explore the opportunities and challenges for future research. More helpfully, we give a prospect for future development of the FPGA-based accelerator.
Abstract: Wireless sensor networks (WSNs), are constantly in demand to process information more rapidly with less energy and area cost. Presently, processor based solutions have difficult to achieve high processing speed with low-power consumption. This paper presents a simple and accurate data processing scheme for low power wireless sensor node, based on reduced number of processing element (PE). The presented model provides a simple recursive structure (SRS) to process the sampled data in the wireless sensor environment and to reduce the power consumption in wireless sensor node. Based on this model, to process the incoming samples and produce a smaller amount of data sufficient to reconstruct the original signal. The ModelSim simulator used to simulate SRS structure. Functional simulation is carried out for the validation of the presented architecture. Xilinx Power Estimator (XPE) tool is used to measure the power consumption. The experimental results show the average power consumption of 91 mW; this is 42% improvement compared to the folded tree architecture.
Abstract: This paper deals with the study of interest in the fields
of Steganography and Steganalysis. Steganography involves hiding
information in a cover media to obtain the stego media in such a
way that the cover media is perceived not to have any embedded
message for its unintended recipients. Steganalysis is the mechanism
of detecting the presence of hidden information in the stego media
and it can lead to the prevention of disastrous security incidents. In
this paper, we provide a critical review of the steganalysis algorithms
available to analyze the characteristics of an image stego media
against the corresponding cover media and understand the process
of embedding the information and its detection. We anticipate that
this paper can also give a clear picture of the current trends in
steganography so that we can develop and improvise appropriate
steganalysis algorithms.
Abstract: Attractive and creative advertisement displays are
often in high demand as they are known to have profound impact on
the commercial market. In the fast advancement of technology,
advertising trend has taken a great leap in attracting more and more
demanding consumers. A low-cost and low-power consumption
flipping advertisement board has been developed in this paper. The
design of the electrical circuit and the controller of the advertisement
board are presented. A microcontroller, a Darlington Pair driver and a
unipolar stepper motor were used to operate the electrical flipping
advertisement board. The proposed system has been implemented
and the hardware has been tested to demonstrate the capability of
displaying multiple advertisements in a panel.