Abstract: Power dissipation increases exponentially during test mode as compared to normal operation of the circuit. In extreme cases, test power is more than twice the power consumed during normal operation mode. Test vector generation scheme is key component in deciding the power hungriness of a circuit during testing. Test vector count and consequent leakage current are functions of test vector generation scheme. Fault based test vector count optimization has been presented in this work. It helps in reducing test vector count and the leakage current. In the presented scheme, test vectors have been reduced by extracting essential child vectors. The scheme has been tested experimentally using stuck at fault models and results ensure the reduction in test vector count.
Abstract: The photovoltaic (PV) panel with no galvanic
isolation system is well known technique in the world which is
effective and delivers power with enhanced efficiency. The PV
generation presented here is for stand-alone system installed in
remote areas when as the resulting power gets connected to electronic
load installation instead of being tied to the grid. Though very small,
even then transformer-less topology is shown to be with leakage in
pico-ampere range. By using PWM technique PWM, leakage current
in different situations is shown. The results shown in this paper show
how the pico-ampere current is reduced to femto-ampere through use
of inductors and capacitors of suitable values of inductor and
capacitors with the load.
Abstract: CNFET has emerged as an alternative material to
silicon for high performance, high stability and low power SRAM
design in recent years. SRAM functions as cache memory in
computers and many portable devices. In this paper, a new SRAM
cell design based on CNFET technology is proposed. The proposed
SRAM cell design for CNFET is compared with SRAM cell designs
implemented with the conventional CMOS and FinFET in terms of
speed, power consumption, stability, and leakage current. The
HSPICE simulation and analysis show that the dynamic power
consumption of the proposed 8T CNFET SRAM cell’s is reduced
about 48% and the SNM is widened up to 56% compared to the
conventional CMOS SRAM structure at the expense of 2% leakage
power and 3% write delay increase.
Abstract: Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-Vt transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.
Abstract: Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.
Abstract: Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.
Abstract: In this paper, FinFET devices are analyzed with
emphasis on sub-threshold leakage current control. This is achieved
through proper biasing of the back gate, and through the use of
asymmetric work functions for the four terminal FinFET devices. We
are also examining different configurations of multiplexers and XOR
gates using transistors of symmetric and asymmetric work functions.
Based on extensive characterization data for MUX circuits, our
proposed configuration using symmetric devices lead to leakage
current and delay improvements of 65% and 47% respectively
compared to results in the literature. For XOR gates, a 90%
improvement in the average leakage current is achieved by using
asymmetric devices. All simulations are based on a 25nm FinFET
technology using the University of Florida UFDG model.
Abstract: This paper presents the experimental results of
leakage current waveforms which appears on porcelain insulator
surface due to existence of artificial pollutants. The tests have been
done using the chemical compounds of NaCl, Na2SiO3, H2SO4, CaO,
Na2SO4, KCl, Al2SO4, MgSO4, FeCl3, and TiO2. The insulator
surface was coated with those compounds and dried. Then, it was
tested in the chamber where the high voltage was applied. Using
correspondence analysis, the result indicated that the fundamental
harmonic of leakage current was very close to the applied voltage
and third harmonic leakage current was close to the yielded leakage
current amplitude. The first harmonic power was correlated to first
harmonic amplitude of leakage current, and third harmonic power
was close to third harmonic one. The chemical compounds of H2SO4
and Na2SiO3 affected to the power factor of around 70%. Both are the
most conductive, due to the power factor drastically increase among
the chemical compounds.