Abstract: An innovative approach to develop modified scaling free CORDIC based two parallel pipelined Multipath Delay Commutator (MDC) FFT and IFFT architectures for radix 22 FFT algorithm is presented. Multipliers and adders are the most important data paths in FFT and IFFT architectures. Multipliers occupy high area and consume more power. In order to optimize the area and power overhead, modified scaling-free CORDIC based complex multiplier is utilized in the proposed design. In general twiddle factor values are stored in RAM block. In the proposed work, modified scaling-free CORDIC based twiddle factor generator unit is used to generate the twiddle factor and efficient switching units are used. In addition to this, four point FFT operations are performed without complex multiplication which helps to reduce area and power in the last two stages of the pipelined architectures. The design proposed in this paper is based on multipath delay commutator method. The proposed design can be extended to any radix 2n based FFT/IFFT algorithm to improve the throughput. The work is synthesized using Synopsys design Compiler using TSMC 90-nm library. The proposed method proves to be better compared to the reference design in terms of area, throughput and power consumption. The comparative analysis of the proposed design with Xilinx FPGA platform is also discussed in the paper.
Abstract: Coordinate Rotation Digital Computer (CORDIC) is a unique digital computing unit intended for the computation of mathematical operations and functions. This paper presents A multi CORDIC processor that integrates different CORDIC architectures on a single FPGA chip and allows the user to select the CORDIC architecture to proceed with based on what he wants to calculate and his needs. Synthesis show that radix 2 CORDIC has the lowest clock delay, radix 8 CORDIC has the highest LUT usage and lowest register usage while Hybrid Radix 4 CORDIC had the highest clock delay.
Abstract: Logarithms reduce products to sums and powers to products; they play an important role in signal processing, communication and information theory. They are primarily
used for hardware calculations, handling multiplications, divisions,
powers, and roots effectively. There are three commonly
used bases for logarithms; the logarithm with base-10 is called
the common logarithm, the natural logarithm with base-e and
the binary logarithm with base-2. This paper demonstrates different
methods of calculation for log2 showing the complexity
of each and finds out the most accurate and efficient besides
giving insights to their hardware design. We present a new
method called Floor Shift for fast calculation of log2, and
then we combine this algorithm with Taylor series to improve
the accuracy of the output, we illustrate that by using two
examples. We finally compare the algorithms and conclude
with our remarks.
Abstract: In a wireless communication system, a
predistorter(PD) is often employed to alleviate nonlinear distortions
due to operating a power amplifier near saturation, thereby improving
the system performance and reducing the interference to adjacent
channels. This paper presents a new adaptive polynomial digital
predistorter(DPD). The proposed DPD uses Coordinate Rotation
Digital Computing(CORDIC) processors and PD process by pipelined
architecture. It is simpler and faster than conventional adaptive
polynomial DPD. The performance of the proposed DPD is proved by
MATLAB simulation.