Abstract: A new digital transceiver circuit for asynchronous frame detection is proposed where both the transmitter and receiver contain all digital components, thereby avoiding possible use of conventional devices like monostable multivibrators with unstable external components such as resistances and capacitances. The proposed receiver circuit, in particular, uses a combinational logic block yielding an output which changes its state as soon as the start bit of a new frame is detected. This, in turn, helps in generating an efficient receiver sampling clock. A data latching circuit is also used in the receiver to latch the recovered data bits in any new frame. The proposed receiver structure is also extended from 4- bit information to any general n data bits within a frame with a common expression for the output of the combinational logic block. Performance of the proposed hardware design is evaluated in terms of time delay, reliability and robustness in comparison with the standard schemes using monostable multivibrators. It is observed from hardware implementation that the proposed circuit achieves almost 33 percent speed up over any conventional circuit.
Abstract: This paper proposes an innovative approach for the Connection Admission Control (CAC) problem. Starting from an abstract network modelling, the CAC problem is formulated in a technology independent fashion allowing the proposed concepts to be applied to any wireless and wired domain. The proposed CAC is decoupled from the other Resource Management procedures, but cooperates with them in order to guarantee the desired QoS requirements. Moreover, it is based on suitable performance measurements which, by using proper predictors, allow to forecast the domain dynamics in the next future. Finally, the proposed CAC control scheme is based on a feedback loop aiming at maximizing a suitable performance index accounting for the domain throughput, whilst respecting a set of constraints accounting for the QoS requirements.