Abstract: In order to manufacture short gap single Si nanowire
(NW) field effect transistor (FET) by imprinting and transferring
method, we introduce the method using Al2O3 sacrificial layer. The
diameters of cylindrical Si NW addressed between Au electrodes by
dielectrophoretic (DEP) alignment method are controlled to 106, 128,
and 148 nm. After imprinting and transfer process, cylindrical Si NW
is embedded in PVP adhesive and dielectric layer. By curing
transferred cylindrical Si NW and Au electrodes on PVP-coated p++ Si
substrate with 200nm-thick SiO2, 3μm gap Si NW FET fabrication
was completed. As the diameter of embedded Si NW increases, the
mobility of FET increases from 80.51 to 121.24 cm2/V·s and the
threshold voltage moves from –7.17 to –2.44 V because the ratio of
surface to volume gets reduced.
Abstract: This paper presents device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET). Simulations show that a narrow nanowire and thin gate oxide is required for good performance, which is expected even for conventional MOSFETs. The gate length also needs to be more than the nanowire diameter to prevent short channel effects. An effect more unique to TFET is the need for abrupt source to channel junction, which is shown to improve the performance. The ambipolar effect suppression by reducing drain doping concentration is also explored and shown to have little or no effect on performance.
Abstract: This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.
Abstract: In this paper, we present a vertical wire NMOS
device fabricated using CMOS compatible processes. The
impact of temperature on various device parameters is
investigated in view of usual increase in surrounding
temperature with device density.
Abstract: In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.
Abstract: In this paper we investigate the electrical
characteristics of a new structure of gate all around strained silicon
nanowire field effect transistors (FETs) with dual dielectrics by
changing the radius (RSiGe) of silicon-germanium (SiGe) wire and
gate dielectric. Indeed the effect of high-κ dielectric on Field Induced
Barrier Lowering (FIBL) has been studied. Due to the higher electron
mobility in tensile strained silicon, the n-type FETs with strained
silicon channel have better drain current compare with the pure Si
one. In this structure gate dielectric divided in two parts, we have
used high-κ dielectric near the source and low-κ dielectric near the
drain to reduce the short channel effects. By this structure short
channel effects such as FIBL will be reduced indeed by increasing
the RSiGe, ID-VD characteristics will be improved. The leakage
current and transfer characteristics, the threshold-voltage (Vt), the
drain induced barrier height lowering (DIBL), are estimated with
respect to, gate bias (VG), RSiGe and different gate dielectrics. For
short channel effects, such as DIBL, gate all around strained silicon
nanowire FET have similar characteristics with the pure Si one while
dual dielectrics can improve short channel effects in this structure.
Abstract: Silicon nanowire (SiNW) based thermoelectric device (TED) has potential applications in areas such as chip level cooling/ energy harvesting. It is a great challenge however, to assemble an efficient device with these SiNW. The presence of parasitic in the form of interfacial electrical resistance will have a significant impact on the performance of the TED. In this work, we explore the effect of the electrical contact resistance on the performance of a TED. Numerical simulations are performed on SiNW to investigate such effects on its cooling performance. Intrinsically, SiNW individually without the unwanted parasitic effect has excellent cooling power density. However, the cooling effect is undermined with the contribution of the electrical contact resistance.
Abstract: This paper presents the design of a ring-shaped tri-axial fore sensor that can be incorporated into the tip of a guidewire for use in minimally invasive surgery (MIS). The designed sensor comprises a ring-shaped structure located at the center of four cantilever beams. The ringdesign allows surgical tools to be easily passed through which largely simplified the integration process. Silicon nanowires (SiNWs) are used aspiezoresistive sensing elementsembeddedon the four cantilevers of the sensor to detect the resistance change caused by the applied load.An integration scheme with new designed guidewire tip structure having two coils at the distal end is presented. Finite element modeling has been employed in the sensor design to find the maximum stress location in order to put the SiNWs at the high stress regions to obtain maximum output. A maximum applicable force of 5 mN is found from modeling. The interaction mechanism between the designed sensor and a steel wire has been modeled by FEM. A linear relationship between the applied load on the steel wire and the induced stress on the SiNWs were observed.
Abstract: In this paper electrical characteristics of various kinds
of multiple-gate silicon nanowire transistors (SNWT) with the
channel length equal to 7 nm are compared. A fully ballistic quantum
mechanical transport approach based on NEGF was employed to
analyses electrical characteristics of rectangular and cylindrical
silicon nanowire transistors as well as a Double gate MOS FET. A
double gate, triple gate, and gate all around nano wires were studied
to investigate the impact of increasing the number of gates on the
control of the short channel effect which is important in nanoscale
devices. Also in the case of triple gate rectangular SNWT inserting
extra gates on the bottom of device can improve the application of
device. The results indicate that by using gate all around structures
short channel effects such as DIBL, subthreshold swing and delay
reduces.