Vertical GAA Silicon Nanowire Transistor with Impact of Temperature on Device Parameters
In this paper, we present a vertical wire NMOS
device fabricated using CMOS compatible processes. The
impact of temperature on various device parameters is
investigated in view of usual increase in surrounding
temperature with device density.
[1] ITRS : http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm
[2] E. Gnani, S. Reggiani, M. Rudan, and G. Baccarani, "Design
considerations and comparative investigation of ultra-thin SOI,
double-gate and cylindrical nanowire FETs", in IEEE ESSDERC
Proceeding, 2006, pp. 371-374.
[3] H. Sakuraba, K. Kinoshita, T. Tanigami, T. Yokoyama, S. Horii, M.
Saitoh, K. Sakiyama, T. Endoh, and F. Masuoka, "New
Three-Dimensional High-Density Stacked-Surrounding Gate Transistor
(S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection
Fabrication Technology without Photolithography Process for Tera-Bits
and Beyong", Jpn. J. Appl. Phys., Vol. 43, No. 4B, 2004, pp. 2217-2219.
[4] A. Ortiz-Conde, F. J. Garcia Sanchez, J. J. Liou, A.Cerdeira, M. Estrada
and Y. Yue, "A review of recent MOSFET threshold voltage",
Microelectron. Rel., Vol. 42, 2002, pp. 583-596.
[5] B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. Q. Lo and D. L.
Kwong, "Vertical silicon-nanowire formation and gate-all-around
MOSFET", IEEE Electron Device Lett., Vol. 29, No. 7, Jul. 2008, pp.
791-794.
[6] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal,
C. H. Tung, K. M Hoe, S. R. Omanpuliyur, D. Tripathi, A. O. Adeyeye,
G. Q. Lo, N. Balasubramanian and D. L. Kwong, "Ultra-Narrow Silicon
Nanowire Gate-All-Around CMOS Devices: Impact of Diameter,
Channel-Orientation and Low Temperature Device Performance", IEDM
2006, pp. 1-4.
[7] M. Lemme1et al., Subthreshold Characteristics of p-type Triple-Gate
MOSFETs, ESSDERC 2003.
[8] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A.
Majumdar, M. Metz, and M. Radosavljevic, "Benchmarking
nanotechnology for high-performance and low-power logic transistor
applications", IEEE Trans. on Nanotechnology, Vol. 4, No. 2, March,
2005, pp. 153-158.
[1] ITRS : http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm
[2] E. Gnani, S. Reggiani, M. Rudan, and G. Baccarani, "Design
considerations and comparative investigation of ultra-thin SOI,
double-gate and cylindrical nanowire FETs", in IEEE ESSDERC
Proceeding, 2006, pp. 371-374.
[3] H. Sakuraba, K. Kinoshita, T. Tanigami, T. Yokoyama, S. Horii, M.
Saitoh, K. Sakiyama, T. Endoh, and F. Masuoka, "New
Three-Dimensional High-Density Stacked-Surrounding Gate Transistor
(S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection
Fabrication Technology without Photolithography Process for Tera-Bits
and Beyong", Jpn. J. Appl. Phys., Vol. 43, No. 4B, 2004, pp. 2217-2219.
[4] A. Ortiz-Conde, F. J. Garcia Sanchez, J. J. Liou, A.Cerdeira, M. Estrada
and Y. Yue, "A review of recent MOSFET threshold voltage",
Microelectron. Rel., Vol. 42, 2002, pp. 583-596.
[5] B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. Q. Lo and D. L.
Kwong, "Vertical silicon-nanowire formation and gate-all-around
MOSFET", IEEE Electron Device Lett., Vol. 29, No. 7, Jul. 2008, pp.
791-794.
[6] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal,
C. H. Tung, K. M Hoe, S. R. Omanpuliyur, D. Tripathi, A. O. Adeyeye,
G. Q. Lo, N. Balasubramanian and D. L. Kwong, "Ultra-Narrow Silicon
Nanowire Gate-All-Around CMOS Devices: Impact of Diameter,
Channel-Orientation and Low Temperature Device Performance", IEDM
2006, pp. 1-4.
[7] M. Lemme1et al., Subthreshold Characteristics of p-type Triple-Gate
MOSFETs, ESSDERC 2003.
[8] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A.
Majumdar, M. Metz, and M. Radosavljevic, "Benchmarking
nanotechnology for high-performance and low-power logic transistor
applications", IEEE Trans. on Nanotechnology, Vol. 4, No. 2, March,
2005, pp. 153-158.
@article{"International Journal of Electrical, Electronic and Communication Sciences:57920", author = "N. Shen and Z. X. Chen and K.D. Buddharaju and H. M. Chua and X. Li and N. Singh and G.Q Lo and D.-L. Kwong", title = "Vertical GAA Silicon Nanowire Transistor with Impact of Temperature on Device Parameters", abstract = "In this paper, we present a vertical wire NMOS
device fabricated using CMOS compatible processes. The
impact of temperature on various device parameters is
investigated in view of usual increase in surrounding
temperature with device density.", keywords = "Gate-all-around, temperature dependence, silicon nanowire", volume = "4", number = "12", pages = "1810-4", }
