Abstract: The contact resistance between source/drain electrodes
and semiconductor layer is an important parameter affecting electron
transporting performance in the thin film transistor (TFT). In this
work, we introduced a transparent and the solution prossable
single-walled carbon nanotube (SWCNT)/Al-doped ZnO nano particle
(AZO NP) bilayer electrodes showing low contact resistance with
indium-oxide (In2O3) sol gel thin film. By inserting low work function
AZO NPs into the interface between the SWCNTs and the In2O3 which
has a high energy barrier, we could obtain an electrical Ohmic contact
between them. Finally, with the SWCNT-AZO NP bilayer electrodes,
we successfully fabricated a TFT showing a field effect mobility of
5.38 cm2/V·s at 250°C.
Abstract: A Silver (Ag) thin film is introduced as a template and
doping source for vertically aligned p–type ZnO nanorods. ZnO
nanorods were grown using an ammonium hydroxide based
hydrothermal process. During the hydrothermal process, the Ag thin
film was dissolved to generate Ag ions in the solution. The Ag ions can
contribute to doping in the wurzite structure of ZnO and the (111)
grain of Ag thin film can be the epitaxial temporal template for the
(0001) plane of ZnO. Hence, Ag–doped p–type ZnO nanorods were
successfully grown on the substrate, which can be an electrode or
semiconductor for the device application. To demonstrate the
potentials of this idea, p–n diode was fabricated and its electrical
characteristics were demonstrated.
Abstract: In order to manufacture short gap single Si nanowire
(NW) field effect transistor (FET) by imprinting and transferring
method, we introduce the method using Al2O3 sacrificial layer. The
diameters of cylindrical Si NW addressed between Au electrodes by
dielectrophoretic (DEP) alignment method are controlled to 106, 128,
and 148 nm. After imprinting and transfer process, cylindrical Si NW
is embedded in PVP adhesive and dielectric layer. By curing
transferred cylindrical Si NW and Au electrodes on PVP-coated p++ Si
substrate with 200nm-thick SiO2, 3μm gap Si NW FET fabrication
was completed. As the diameter of embedded Si NW increases, the
mobility of FET increases from 80.51 to 121.24 cm2/V·s and the
threshold voltage moves from –7.17 to –2.44 V because the ratio of
surface to volume gets reduced.