Abstract: In this paper we investigate the electrical
characteristics of a new structure of gate all around strained silicon
nanowire field effect transistors (FETs) with dual dielectrics by
changing the radius (RSiGe) of silicon-germanium (SiGe) wire and
gate dielectric. Indeed the effect of high-κ dielectric on Field Induced
Barrier Lowering (FIBL) has been studied. Due to the higher electron
mobility in tensile strained silicon, the n-type FETs with strained
silicon channel have better drain current compare with the pure Si
one. In this structure gate dielectric divided in two parts, we have
used high-κ dielectric near the source and low-κ dielectric near the
drain to reduce the short channel effects. By this structure short
channel effects such as FIBL will be reduced indeed by increasing
the RSiGe, ID-VD characteristics will be improved. The leakage
current and transfer characteristics, the threshold-voltage (Vt), the
drain induced barrier height lowering (DIBL), are estimated with
respect to, gate bias (VG), RSiGe and different gate dielectrics. For
short channel effects, such as DIBL, gate all around strained silicon
nanowire FET have similar characteristics with the pure Si one while
dual dielectrics can improve short channel effects in this structure.
Abstract: In this paper electrical characteristics of various kinds
of multiple-gate silicon nanowire transistors (SNWT) with the
channel length equal to 7 nm are compared. A fully ballistic quantum
mechanical transport approach based on NEGF was employed to
analyses electrical characteristics of rectangular and cylindrical
silicon nanowire transistors as well as a Double gate MOS FET. A
double gate, triple gate, and gate all around nano wires were studied
to investigate the impact of increasing the number of gates on the
control of the short channel effect which is important in nanoscale
devices. Also in the case of triple gate rectangular SNWT inserting
extra gates on the bottom of device can improve the application of
device. The results indicate that by using gate all around structures
short channel effects such as DIBL, subthreshold swing and delay
reduces.