Abstract: The mechanism of nickel (Ni) metallization in silicon-germanium (Si0.5Ge0.5) alloy nanowire (NW) was studied. Transmission electron microscope imaging with in-situ annealing was conducted at temperatures of 200oC to 600°C. During rapid formation of Ni germanosilicide, loss of material from from the SiGe NW occurred which led to the formation of a thin Ni germanosilicide filament and eventual void. Energy dispersive X-ray spectroscopy analysis along the SiGe NW before and after annealing determined that Ge atoms tend to out-diffuse from the Ni germanosilicide towards the Ni source in the course of annealing. A model for the Ni germanosilicide formation in SiGe NW is proposed to explain this observation.
Abstract: We have developed an analytic model for the radial pn-junction in a nanowire (NW) core-shell structure utilizing as a new
building block in different semiconductor devices. The potential distribution through the p-n-junction is calculated and the analytical expressions are derived to compute the depletion region widths. We
show that the widths of space charge layers, surrounding the core, are
the functions of core radius, which is the manifestation of so called classical size effect. The relationship between the depletion layer width and the built-in potential in the asymptotes of infinitely large
core radius transforms to square-root dependence specific for conventional planar p-n-junctions. The explicit equation is derived to
compute the capacitance of radial p-n-junction. The current-voltage behavior is also carefully determined taking into account the “short
base" effects.
Abstract: In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.