Suppressing Ambipolar Conduction Using Dual Material Gate in Tunnel-FETs Having Heavily Doped Drain

In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.





References:
[1] A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic,” Proc. IEEE, vol. 98, no. 12, pp. 2095–2110, Dec. 2010.
[2] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy efficient electronic switches,” Nature, vol. 479, no.7373, pp. 329–337, Nov. 2011.
[3] Y. Khatami and K. Banerjee, “Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits,” IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2752–2761, Nov. 2009.
[4] A. C. Seabaugh and H. Lu, “Tunnel field-effect transistors – update,” IEEE International Conference on Solid-State and Integrated Circuit Technology, no. 12, Oct. 2014, pp. 1-4.
[5] A. S. Verhulst, W. G. Vandenberghe, K. Maex, G. Groeseneken, “Tunnel field-effect transistor without gate–drain overlap,” Applied Physics Letters, vol. 91, no. 5, pp. 053102-053103, Jul. 2007.
[6] J. Wan, C. Le Royer, A. Zaslavsky and S. Cristoloveanu, “SOI TFETs: Suppression of ambipolar leakage and low-frequency noise behavior,” Proc. European Solid-State Device Research Conference (ESSDERC), 2010, pp.341 – 344.
[7] K. Boucart and A. M. Ionescu, “Double gate tunnel FET with high-k gate dielectric,” IEEE Trans.on Electron Devices, vol. 54, no. 7, pp. 1725-1733, Jul. 2007.
[8] A. Hraziia, C. Andrei, A. Vladimirescu, A. Amara, C. Anghel, “An analysis on the ambipolar current in Si double-gate tunnel FETs,” Solid-State Electronics, vol. 70, pp. 67-72, Apr. 2012.
[9] W. Y. Choi and W. Lee, “Hetero-gate-dielectric tunnelling field effect transistors,” IEEE Trans. on Electron Devices, vol. 57, no. 9, pp. 2317-2319, Sep. 2010.
[10] D. B. Abdi and M. J. Kumar, “Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain,” IEEE Journal of Electron Devices Society, no. 6, vol.2, pp. 187-190, Nov. 2014.
[11] D. B. Abdi and M. J. Kumar, “Dielectric Modulated Overlapping Gate-on-Drain Tunnel-FET as a Label-Free Biosensor,” Superlattices and Microstructures, vol.86, pp.198–202, October 2015.
[12] M. J Kumar and A. Chaudhry, “Two-Dimensional Analytical Modeling of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET and Evidence for Diminished Short-Channel Effects,” IEEE Trans. on Electron Devices, vol. 51, pp. 569-574, April 2004.
[13] G. V. Reddy and M. J. Kumar, “A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET – Two-dimensional Analytical Modeling and Simulation,” IEEE Trans. on Nanotechnology, vol. 4, pp. 260 - 268, Mar. 2005.
[14] A. Chaudhry and M. J. Kumar, “Investigation of the Novel Attributes of a Fully Depleted (FD) Dual-Material Gate (DMG) SOI MOSFET,” IEEE Trans. on Electron Devices, vol. 51, pp. 1463-1467, Sep. 2004.
[15] R. S. Saxena and M. J. Kumar “Dual Material Gate Technique for Enhanced Transconductance and Breakdown Voltage of Trench Power MOSFETs,” IEEE Trans. on Electron Devices, vol. 56, pp. 517-522, Mar. 2009.
[16] S. Saurabh and M. J. Kumar, “Investigation of the Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field Effect Transistor,” IEEE Trans. on Electron Devices, vol. 58, pp. 404-410, Feb. 2011.
[17] R. Vishnoi and M. J. Kumar, “Compact Analytical Model of Dual Material Gate Tunneling Field Effect Transistor using Interband Tunneling and Channel Transport,” IEEE Trans. on Electron Devices, vol. 61, no. 6, pp. 1936 - 1942, Jun. 2014.
[18] R. Vishnoi and M. J. Kumar, “A Pseudo 2D-analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET,” IEEE Trans. on Electron Devices, vol. 61, pp. 2264-2270, Jul. 2014.
[19] M. S. Ram and D. B. Abdi, “Dopingless Tunnel FET Hetero-Gate-Dielectric: Design and Analysis” 2nd IEEE International Conference on Emerging Electronics, Dec., 2014, pp. 1-4.
[20] N. V. Nagavarapu, R. Jhaveri, and J. C. S. Woo, “The tunnel source (PNPN) n-MOSFET: A novel high performance transistor,” IEEE Trans. Electron Devices, vol. 55, no. 4, pp. 1013-1019, Apr. 2008.
[21] D. B. Abdi and M. J. Kumar, “In-built N+ Pocket PNPN Tunnel Field-Effect Transistor,” IEEE Electron Device Letters, vol.35, no. 12, pp. 1170 - 1172, Dec. 2014.
[22] A. Tura, Z. Zhang, P. Liu, Y-H. Xie, and J.C.S. Woo, “Vertical silicon p-n-p-n tunnel nMOSFET with MBE-grown tunneling junction,” IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 1907-1913, Jul. 2011.
[23] H.-Y. Chang, B. Adams, P.-Y. Chien, J. Li, and J.C.S. Woo, “Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing,” IEEE Trans. Electron Devices, vol. 60, no. 1, pp. 92-96, Jan. 2013.
[24] M. S. Ram and D. B. Abdi, “Single grain boundary tunnel field effect transistors on recrystallized polycrystalline silicon: Proposal and investigation,” IEEE Electron Device Lett., vol. 35, no. 10, pp. 989–991, Oct. 2014.
[25] S. Cho, and I. M. Kang, “Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics,” Current Applied Physics, vol. 12, issue. 3, pp. 673-677, May 2012.
[26] D. B. Abdi and M. J. Kumar, “PNPN Tunnel FET with Controllable Drain Side Tunnel Barrier Width: Proposal and Analysis,” Superlattices and Microstructures, vol.86, pp.121–125, October 2015.
[27] M. S. Ram and D. B. Abdi, “Dopingless PNPN Tunnel FET with Improved Performance: Design and Analysis”, Superlattices and Microstructures, vol. 82, pp. 430-437, June 2015.
[28] M. S. Ram and D. B. Abdi, “Single Grain Boundary Dopingless PNPN Tunnel FET on Recrystallized Polysilicon: Proposal and Theoretical Analysis” IEEE Journal of Electron Devices Society, vol.3, no. 3, pp. 291-296, Jan, 2015.
[29] ATLAS Device Simulation Software, Silvaco Int., Santa Clara, CA, USA, 2014.
[30] A. Mallik and A. Chattopadhyay, “Drain-Dependence of Tunnel Field-Effect Transistor Characteristics: The Role of the Channel,” IEEE Trans. on Electron Devices, vol. 58, no. 12, pp. 4250-4257, Dec. 2011.
[31] A. Mallik and A. Chattopadhyay, “Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications,” IEEE Trans. on Electron Devices, vol.59, no.4, pp.888-894, Apr. 2012.