Performance Enhancement of Motion Estimation Using SSE2 Technology
Motion estimation is the most computationally
intensive part in video processing. Many fast motion estimation
algorithms have been proposed to decrease the computational
complexity by reducing the number of candidate motion vectors.
However, these studies are for fast search algorithms themselves while
almost image and video compressions are operated with software
based. Therefore, the timing constraints for running these motion
estimation algorithms not only challenge for the video codec but also
overwhelm for some of processors. In this paper, the performance of
motion estimation is enhanced by using Intel's Streaming SIMD
Extension 2 (SSE2) technology with Intel Pentium 4 processor.
[1] T. Wiegand, G. J. Sullivan, G. Bjontegaard and A. Luthra, "Overview of
the H.264/AVC Video Coding Standard," IEEE Trans. Circuits. Syst.
Video Technol., vol. 13, pp. 560-576, July 2003.
[2] X. Jing and L. P. Chau, "An Efficient Three-Step Search Algorithm for
Block Motion Estimation," IEEE Trans. Mutimedia, vol. 6, pp. 435-438,
June 2004.
[3] D. Talla, L. K. John and D. Burger, "Bottenecks in Multimedia Processing
with SIMD Style Extensions and Architectural Enhancements," IEEE
Trans. Computers, vol. 52, pp. 1015-1031, August 2003.
[4] "Using SSE2 in Motion Compensation for Video Decoding and
Encoding," Intel Application Note, AP-942.
[5] A. Peleg and U. Weiser, "MMX Technology Extension to the Intel
Architecture," IEEE Micro, August 1996.
[6] G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P.
Roussel, "The Microarchitecture of the Pentium 4 Processor", Intel
Technology Journal Q1, 2001.
[1] T. Wiegand, G. J. Sullivan, G. Bjontegaard and A. Luthra, "Overview of
the H.264/AVC Video Coding Standard," IEEE Trans. Circuits. Syst.
Video Technol., vol. 13, pp. 560-576, July 2003.
[2] X. Jing and L. P. Chau, "An Efficient Three-Step Search Algorithm for
Block Motion Estimation," IEEE Trans. Mutimedia, vol. 6, pp. 435-438,
June 2004.
[3] D. Talla, L. K. John and D. Burger, "Bottenecks in Multimedia Processing
with SIMD Style Extensions and Architectural Enhancements," IEEE
Trans. Computers, vol. 52, pp. 1015-1031, August 2003.
[4] "Using SSE2 in Motion Compensation for Video Decoding and
Encoding," Intel Application Note, AP-942.
[5] A. Peleg and U. Weiser, "MMX Technology Extension to the Intel
Architecture," IEEE Micro, August 1996.
[6] G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P.
Roussel, "The Microarchitecture of the Pentium 4 Processor", Intel
Technology Journal Q1, 2001.
@article{"International Journal of Information, Control and Computer Sciences:49355", author = "Trung Hieu Tran and Hyo-Moon Cho and Sang-Bock Cho", title = "Performance Enhancement of Motion Estimation Using SSE2 Technology", abstract = "Motion estimation is the most computationally
intensive part in video processing. Many fast motion estimation
algorithms have been proposed to decrease the computational
complexity by reducing the number of candidate motion vectors.
However, these studies are for fast search algorithms themselves while
almost image and video compressions are operated with software
based. Therefore, the timing constraints for running these motion
estimation algorithms not only challenge for the video codec but also
overwhelm for some of processors. In this paper, the performance of
motion estimation is enhanced by using Intel's Streaming SIMD
Extension 2 (SSE2) technology with Intel Pentium 4 processor.", keywords = "Motion Estimation, Full Search, Three StepSearch, MMX/SSE/SSE2 Technologies, SIMD.", volume = "2", number = "4", pages = "1011-4", }