An Optimization Tool-Based Design Strategy Applied to Divide-by-2 Circuits with Unbalanced Loads
This paper describes an optimization tool-based
design strategy for a Current Mode Logic CML divide-by-2 circuit.
Representing a building block for output frequency generation in a
RFID protocol based-frequency synthesizer, the circuit was designed
to minimize the power consumption for driving of multiple loads
with unbalancing (at transceiver level). Implemented with XFAB
XC08 180 nm technology, the circuit was optimized through
MunEDA WiCkeD tool at Cadence Virtuoso Analog Design
Environment ADE.
[1] H. Zargar, M. Kamarei, and M. Tayarani, “Design and stability analysis
of an injection-locked frequency divider by two”, 2010, 18th Iran. Conf.
Electr. Eng., vol. 1, pp. 63–67, May 2010.
[2] B. Razavi, Design of Integrated Circuits for Optcial Communications,
McGraw-Hill, 2003.
[3] O. B. M. Abdulkarim, “Design and optimization of MOS CML circuits”,
Master’s thesis, Carleton University, 2006.
[4] A. Tajalli, E. Vittoz, Y. Leblebici and E. J. Brauer, “Ultra Low Power
Subthreshold MOS Current Mode Logic Circuits Using a Novel Load
Device Concept”, IEEE circuits conference 2007, ESSCIRC 2007. 33rd
European, pp. 304-307.
[5] F. D. J. Rogers, and C. Plett, Integrated Circuit Design for High-Speed
Frequency Synthesis. Artech House Microwave Library, 2006.
[6] WiCkeD User Manual, Version 6.1, MunEDA GmbH, Munich
Germany.
[1] H. Zargar, M. Kamarei, and M. Tayarani, “Design and stability analysis
of an injection-locked frequency divider by two”, 2010, 18th Iran. Conf.
Electr. Eng., vol. 1, pp. 63–67, May 2010.
[2] B. Razavi, Design of Integrated Circuits for Optcial Communications,
McGraw-Hill, 2003.
[3] O. B. M. Abdulkarim, “Design and optimization of MOS CML circuits”,
Master’s thesis, Carleton University, 2006.
[4] A. Tajalli, E. Vittoz, Y. Leblebici and E. J. Brauer, “Ultra Low Power
Subthreshold MOS Current Mode Logic Circuits Using a Novel Load
Device Concept”, IEEE circuits conference 2007, ESSCIRC 2007. 33rd
European, pp. 304-307.
[5] F. D. J. Rogers, and C. Plett, Integrated Circuit Design for High-Speed
Frequency Synthesis. Artech House Microwave Library, 2006.
[6] WiCkeD User Manual, Version 6.1, MunEDA GmbH, Munich
Germany.
@article{"International Journal of Electrical, Electronic and Communication Sciences:70123", author = "Agord M. Pinto Jr. and Yuzo Iano and Leandro T. Manera and Raphael R. N. Souza", title = "An Optimization Tool-Based Design Strategy Applied to Divide-by-2 Circuits with Unbalanced Loads", abstract = "This paper describes an optimization tool-based
design strategy for a Current Mode Logic CML divide-by-2 circuit.
Representing a building block for output frequency generation in a
RFID protocol based-frequency synthesizer, the circuit was designed
to minimize the power consumption for driving of multiple loads
with unbalancing (at transceiver level). Implemented with XFAB
XC08 180 nm technology, the circuit was optimized through
MunEDA WiCkeD tool at Cadence Virtuoso Analog Design
Environment ADE.", keywords = "Divide-by-2 circuit, CMOS technology, PLL phase
locked-loop, optimization tool, CML current mode logic, RF
transceiver.", volume = "9", number = "6", pages = "521-5", }