Fully Parameterizable FPGA based Crypto-Accelerator
In this paper, RSA encryption algorithm and its hardware
implementation in Xilinx-s Virtex Field Programmable Gate
Arrays (FPGA) is analyzed. The issues of scalability, flexible performance,
and silicon efficiency for the hardware acceleration of
public key crypto systems are being explored in the present work.
Using techniques based on the interleaved math for exponentiation,
the proposed RSA calculation architecture is compared to existing
FPGA-based solutions for speed, FPGA utilization, and scalability.
The paper covers the RSA encryption algorithm, interleaved multiplication,
Miller Rabin algorithm for primality test, extended Euclidean
math, basic FPGA technology, and the implementation details of
the proposed RSA calculation architecture. Performance of several
alternative hardware architectures is discussed and compared. Finally,
conclusion is drawn, highlighting the advantages of a fully flexible
& parameterized design.
[1] Lu, Jing, and Qian Wan, . Implementing a 1024 Bit RSA on
FPGA. 03 May 2003. Dept. of CSE., Washington U. 21 Jan. 2008
<www.arl.wustl.edu/˜jl1/education/cs502/doc/report.doc>.
[2] Amanor, David Narh, comp. Efficient Hardware Architectures
For Modular Multiplication On FPGAs. 19 Feb. 2005. The
University of Applied Sciences CityplaceOffenburg. 07 Dec. 2007
<www.crypto.rub.de/imperia/md/content/texte/theses/dnamanorthesis.pdf>.
[3] "Division (Digital)." Wikipedia. dateMonth4Day17Year200717
Apr. 2007. Wikipedia. dateMonth12Day12Year200712 Dec. 2007
<http://en.wikipedia.org/wiki/Restoring division#Restoring division>.
[4] G. Miller, Riemann-s Hypothesis and Tests for Primality. Proceeding sof
the 7th Annual ACM Symposium on the Theory of Computing, May
1975.
[5] M. Rabin, Probabilistic Algorithms for Primality Testing. Journal of
Number Theory, Dec. 1980.
[6] Wu, C.-L., Lou, D.-C., Chang, T.-J.," Fast Binary Multiplication
Method forModular Exponentiation." Tanet, 2005. 22 Nov. 2007.
<tanet2005.nchu.edu.tw/session/TANet2005Sessiondetail.pdf>.
[7] "DS257",Linear Feedback Shift Register v3.0. V-1, date-
Month3Day28Year200328 MAR 2003. Xilinx. 04 Jan. 2008.
[8] Wockinger, thomas. High-Speed RSA Implementation.07 Jan
2005, Institute of applied information., Graz U. 27 Nov 2007
<www.iaik.tugraz.at/teaching/11 diplomarbeiten/archive/woeckinger.pdf>.
[1] Lu, Jing, and Qian Wan, . Implementing a 1024 Bit RSA on
FPGA. 03 May 2003. Dept. of CSE., Washington U. 21 Jan. 2008
<www.arl.wustl.edu/˜jl1/education/cs502/doc/report.doc>.
[2] Amanor, David Narh, comp. Efficient Hardware Architectures
For Modular Multiplication On FPGAs. 19 Feb. 2005. The
University of Applied Sciences CityplaceOffenburg. 07 Dec. 2007
<www.crypto.rub.de/imperia/md/content/texte/theses/dnamanorthesis.pdf>.
[3] "Division (Digital)." Wikipedia. dateMonth4Day17Year200717
Apr. 2007. Wikipedia. dateMonth12Day12Year200712 Dec. 2007
<http://en.wikipedia.org/wiki/Restoring division#Restoring division>.
[4] G. Miller, Riemann-s Hypothesis and Tests for Primality. Proceeding sof
the 7th Annual ACM Symposium on the Theory of Computing, May
1975.
[5] M. Rabin, Probabilistic Algorithms for Primality Testing. Journal of
Number Theory, Dec. 1980.
[6] Wu, C.-L., Lou, D.-C., Chang, T.-J.," Fast Binary Multiplication
Method forModular Exponentiation." Tanet, 2005. 22 Nov. 2007.
<tanet2005.nchu.edu.tw/session/TANet2005Sessiondetail.pdf>.
[7] "DS257",Linear Feedback Shift Register v3.0. V-1, date-
Month3Day28Year200328 MAR 2003. Xilinx. 04 Jan. 2008.
[8] Wockinger, thomas. High-Speed RSA Implementation.07 Jan
2005, Institute of applied information., Graz U. 27 Nov 2007
<www.iaik.tugraz.at/teaching/11 diplomarbeiten/archive/woeckinger.pdf>.
@article{"International Journal of Information, Control and Computer Sciences:55911", author = "Iqbalur Rahman and Miftahur Rahman and Abul L Haque and Mostafizur Rahman and ", title = "Fully Parameterizable FPGA based Crypto-Accelerator", abstract = "In this paper, RSA encryption algorithm and its hardware
implementation in Xilinx-s Virtex Field Programmable Gate
Arrays (FPGA) is analyzed. The issues of scalability, flexible performance,
and silicon efficiency for the hardware acceleration of
public key crypto systems are being explored in the present work.
Using techniques based on the interleaved math for exponentiation,
the proposed RSA calculation architecture is compared to existing
FPGA-based solutions for speed, FPGA utilization, and scalability.
The paper covers the RSA encryption algorithm, interleaved multiplication,
Miller Rabin algorithm for primality test, extended Euclidean
math, basic FPGA technology, and the implementation details of
the proposed RSA calculation architecture. Performance of several
alternative hardware architectures is discussed and compared. Finally,
conclusion is drawn, highlighting the advantages of a fully flexible
& parameterized design.", keywords = "Crypto Accelerator, FPGA, Public Key Cryptography,RSA.", volume = "3", number = "11", pages = "2604-7", }