Two-dimensional Analytical Drain Current Model for Multilayered-Gate Material Engineered Trapezoidal Recessed Channel(MLGME-TRC) MOSFET: a Novel Design
In this paper, for the first time, a two-dimensional
(2D) analytical drain current model for sub-100 nm multi-layered
gate material engineered trapezoidal recessed channel (MLGMETRC)
MOSFET: a novel design is presented and investigated using
ATLAS and DEVEDIT device simulators, to mitigate the large gate
leakages and increased standby power consumption that arise due to
continued scaling of SiO2-based gate dielectrics. The twodimensional
(2D) analytical model based on solution of Poisson-s
equation in cylindrical coordinates, utilizing the cylindrical
approximation, has been developed which evaluate the surface
potential, electric field, drain current, switching metric: ION/IOFF
ratio and transconductance for the proposed design. A good
agreement between the model predictions and device simulation
results is obtained, verifying the accuracy of the proposed analytical
model.
[1] S.A. Campbell, D.C. Gilmer, X. Wang, M. Hsieh, H-S. Kim, W.L.
Gladfelter and J. Yan , "MOSFET transistors fabricated with high
permittivity TiO2 dielectrics" IEEE Trans. Electron Devices vol. 44,
pp.104-109, (1997).
[2] W. Tsai et a,l "Performance comparison of sub 1 nm sputtered TiN
HfO2 nMOS and pMOSFETs" IEDM Tech., Dig. 311-314, (2003).
[3] H. Kimura, J. Mizuki, S. Kamiyama and H. Suzuki, "Extended x-ray
absorption fine structure analysis of the difference in local structure of
tantalum oxide capacitor films produced by various annealing methods"
Appl. Phys. Lett. Vol. 66, pp.2209-2211, (1995).
[4] J-L Autran, D. Munteanu, M. Houssa, K. C. Coulie and A. Said,
"Performance degradation induced by fringing field-induced barrier
lowering and parasitic charge in double-gate metal-oxide
semiconductor field-effect transistors with high-ê dielectrics" Japan. J.
Appl. Phys. Vol. 44, 8362-6, (2005).
[5] S.J. Lee, C.H. Choi, A. Kamath, R. Clark and D.L. Kwong, "
Characterization and reliability of dual high-k gate dielectric stack
(poly-Si-HfO2-SiO2) prepared by in situ RTCVD process for systemon-
chip applications" IEEE Electron Device Lett. Vol. 24, 105-107,
(2003).
[6] T. Kauerauf, B. Govoreanu, R. Degraeve, G. Groeseneken and H. Maes,
"Scaling CMOS: finding the gate stack with the lowest leakage current"
Solid-State Electron. Vol. 49, 695-701, (2005).
[7] B.Cheng, M. Cao, R. Rao, A. Inani, P.V. Voorde, W.M. Greene, J.M.C.
Stork, Z. Yu, P.M. Zeitoff and J.C.S. Woo , "The impact of high-k gate
dielectrics and metal gate electrodes on sub-100 nm MOSFETs" IEEE
Trans. Electron. Devices Vol. 46, pp. 1537, (1999).
[8] J. Zhang, J.S. Yuan and Y. Ma "Modeling short channel effect on highk
and stacked gate MOSFETs" Solid-State Electron. Vol.44, pp.
2089, (2000).
[9] P.Malik, S.P.Kumar, R.Chaujar, M.Gupta, R.S.Gupta, "GATE
MATERIAL ENGINEERED-TRAPIZIODAL RECESSED CHANNEL
MOSFET FOR HIGH-PERFORMANCE ANALOG AND RF
APPLICATIONS", Microwave and optical technology letters, Vol.52,
march 2010.
[10] P.H. Bricout and E. Dubois "Short-channel effect immunity and current
capability of sub-0.1-micron MOSFETs using a recessed channel" IEEE
Trans. Electron. Devices Vol.43, pp.1251 (1996).
[11] H. Ren and Y. Hao "The influence of geometric structure on the hotcarrier-
effect immunity for deep-sub-micron grooved gate PMOSFET
Solid-State Electron". Vol.46, pp. 665 (2002).
[12] ATLAS: 3-D and DEVEDIT: 3D Device Simulator SILVACO
International (2002).
[13] X.J. Zhang, H.X. Ren, Q. Feng and Y. Hao, Chin. J. Semiconductors,
Vol.25, pp. 441, (2004) (in chinese)
[14] N.D. Arora, R.Rios, C-L Huang and K. Raol,"PCIM: A Physically
Short-Channel IGFET Model for Circuit Simulation" IEEE Trans.
Electron Devices, Vol.41, June 1994.
[1] S.A. Campbell, D.C. Gilmer, X. Wang, M. Hsieh, H-S. Kim, W.L.
Gladfelter and J. Yan , "MOSFET transistors fabricated with high
permittivity TiO2 dielectrics" IEEE Trans. Electron Devices vol. 44,
pp.104-109, (1997).
[2] W. Tsai et a,l "Performance comparison of sub 1 nm sputtered TiN
HfO2 nMOS and pMOSFETs" IEDM Tech., Dig. 311-314, (2003).
[3] H. Kimura, J. Mizuki, S. Kamiyama and H. Suzuki, "Extended x-ray
absorption fine structure analysis of the difference in local structure of
tantalum oxide capacitor films produced by various annealing methods"
Appl. Phys. Lett. Vol. 66, pp.2209-2211, (1995).
[4] J-L Autran, D. Munteanu, M. Houssa, K. C. Coulie and A. Said,
"Performance degradation induced by fringing field-induced barrier
lowering and parasitic charge in double-gate metal-oxide
semiconductor field-effect transistors with high-ê dielectrics" Japan. J.
Appl. Phys. Vol. 44, 8362-6, (2005).
[5] S.J. Lee, C.H. Choi, A. Kamath, R. Clark and D.L. Kwong, "
Characterization and reliability of dual high-k gate dielectric stack
(poly-Si-HfO2-SiO2) prepared by in situ RTCVD process for systemon-
chip applications" IEEE Electron Device Lett. Vol. 24, 105-107,
(2003).
[6] T. Kauerauf, B. Govoreanu, R. Degraeve, G. Groeseneken and H. Maes,
"Scaling CMOS: finding the gate stack with the lowest leakage current"
Solid-State Electron. Vol. 49, 695-701, (2005).
[7] B.Cheng, M. Cao, R. Rao, A. Inani, P.V. Voorde, W.M. Greene, J.M.C.
Stork, Z. Yu, P.M. Zeitoff and J.C.S. Woo , "The impact of high-k gate
dielectrics and metal gate electrodes on sub-100 nm MOSFETs" IEEE
Trans. Electron. Devices Vol. 46, pp. 1537, (1999).
[8] J. Zhang, J.S. Yuan and Y. Ma "Modeling short channel effect on highk
and stacked gate MOSFETs" Solid-State Electron. Vol.44, pp.
2089, (2000).
[9] P.Malik, S.P.Kumar, R.Chaujar, M.Gupta, R.S.Gupta, "GATE
MATERIAL ENGINEERED-TRAPIZIODAL RECESSED CHANNEL
MOSFET FOR HIGH-PERFORMANCE ANALOG AND RF
APPLICATIONS", Microwave and optical technology letters, Vol.52,
march 2010.
[10] P.H. Bricout and E. Dubois "Short-channel effect immunity and current
capability of sub-0.1-micron MOSFETs using a recessed channel" IEEE
Trans. Electron. Devices Vol.43, pp.1251 (1996).
[11] H. Ren and Y. Hao "The influence of geometric structure on the hotcarrier-
effect immunity for deep-sub-micron grooved gate PMOSFET
Solid-State Electron". Vol.46, pp. 665 (2002).
[12] ATLAS: 3-D and DEVEDIT: 3D Device Simulator SILVACO
International (2002).
[13] X.J. Zhang, H.X. Ren, Q. Feng and Y. Hao, Chin. J. Semiconductors,
Vol.25, pp. 441, (2004) (in chinese)
[14] N.D. Arora, R.Rios, C-L Huang and K. Raol,"PCIM: A Physically
Short-Channel IGFET Model for Circuit Simulation" IEEE Trans.
Electron Devices, Vol.41, June 1994.
@article{"International Journal of Electrical, Electronic and Communication Sciences:55347", author = "Priyanka Malik A and Rishu Chaujar B and Mridula Gupta C and R.S. Gupta D", title = "Two-dimensional Analytical Drain Current Model for Multilayered-Gate Material Engineered Trapezoidal Recessed Channel(MLGME-TRC) MOSFET: a Novel Design", abstract = "In this paper, for the first time, a two-dimensional
(2D) analytical drain current model for sub-100 nm multi-layered
gate material engineered trapezoidal recessed channel (MLGMETRC)
MOSFET: a novel design is presented and investigated using
ATLAS and DEVEDIT device simulators, to mitigate the large gate
leakages and increased standby power consumption that arise due to
continued scaling of SiO2-based gate dielectrics. The twodimensional
(2D) analytical model based on solution of Poisson-s
equation in cylindrical coordinates, utilizing the cylindrical
approximation, has been developed which evaluate the surface
potential, electric field, drain current, switching metric: ION/IOFF
ratio and transconductance for the proposed design. A good
agreement between the model predictions and device simulation
results is obtained, verifying the accuracy of the proposed analytical
model.", keywords = "ATLAS, DEVEDIT, NJD, MLGME- TRCMOSFET.", volume = "4", number = "4", pages = "723-5", }