Abstract: This paper presents a new circuit arrangement for a
current-mode Wheatstone bridge that is suitable for low-voltage
integrated circuits implementation. Compared to the other proposed
circuits, this circuit features severe reduction of the elements number,
low supply voltage (1V) and low power consumption (
Abstract: In this paper, a double balanced radio frequency multiplier
is presented which is customized for transmitted reference
ultra wideband (UWB) receivers. The multiplier uses 90nm model
parameters and exploits compensating transistors to provide controllable
gain for a Gilbert core. After performing periodic and quasiperiodic
non linear analyses the RF mixer (multiplier) achieves a
voltage conversion gain of 16 dB and a DSB noise figure of 8.253
dB with very low power consumption. A high degree of LO to RF
isolation (in the range of -94dB), RF to IF isolation (in the range of
-95dB) and LO to IF isolation (in the range of -143dB) is expected
for this design with an input-referred IP3 point of -1.93 dBm and an
input referred 1 dB compression point of -10.67dBm. The amount of
noise at the output is 7.7 nV/√Hz when the LO input is driven by
a 10dBm signal. The mixer manifests better results when compared
with other reported multiplier circuits and its Zero-IF performance
ensures its applicability as TR-UWB multipliers.
Abstract: A 1V, 1GHz low noise amplifier (LNA) has been designed and simulated using Spectre simulator in a standard TSMC 0.18um CMOS technology.With low power and noise optimization techniques, the amplifier provides a gain of 24 dB, a noise figure of only 1.2 dB, power dissipation of 14 mW from a 1 V power supply.
Abstract: As chip manufacturing technology is suddenly on the
threshold of major evaluation, which shrinks chip in size and
performance, LFSR (Linear Feedback Shift Register) is implemented
in layout level which develops the low power consumption chip,
using recent CMOS, sub-micrometer layout tools. Thus LFSR
counter can be a new trend setter in cryptography and is also
beneficial as compared to GRAY & BINARY counter and variety of
other applications.
This paper compares 3 architectures in terms of the hardware
implementation, CMOS layout and power consumption, using
Microwind CMOS layout tool. Thus it provides solution to a low
power architecture implementation of LFSR in CMOS VLSI.
Abstract: This paper discusses a new, systematic approach to
the synthesis of a NP-hard class of non-regenerative Boolean
networks, described by FON[FOFF]={mi}[{Mi}], where for every
mj[Mj]∈{mi}[{Mi}], there exists another mk[Mk]∈{mi}[{Mi}], such
that their Hamming distance HD(mj, mk)=HD(Mj, Mk)=O(n), (where
'n' represents the number of distinct primary inputs). The method
automatically ensures exact minimization for certain important selfdual
functions with 2n-1 points in its one-set. The elements meant for
grouping are determined from a newly proposed weighted incidence
matrix. Then the binary value corresponding to the candidate pair is
correlated with the proposed binary value matrix to enable direct
synthesis. We recommend algebraic factorization operations as a post
processing step to enable reduction in literal count. The algorithm
can be implemented in any high level language and achieves best
cost optimization for the problem dealt with, irrespective of the
number of inputs. For other cases, the method is iterated to
subsequently reduce it to a problem of O(n-1), O(n-2),.... and then
solved. In addition, it leads to optimal results for problems exhibiting
higher degree of adjacency, with a different interpretation of the
heuristic, and the results are comparable with other methods.
In terms of literal cost, at the technology independent stage, the
circuits synthesized using our algorithm enabled net savings over
AOI (AND-OR-Invert) logic, AND-EXOR logic (EXOR Sum-of-
Products or ESOP forms) and AND-OR-EXOR logic by 45.57%,
41.78% and 41.78% respectively for the various problems.
Circuit level simulations were performed for a wide variety of
case studies at 3.3V and 2.5V supply to validate the performance of
the proposed method and the quality of the resulting synthesized
circuits at two different voltage corners. Power estimation was
carried out for a 0.35micron TSMC CMOS process technology. In
comparison with AOI logic, the proposed method enabled mean
savings in power by 42.46%. With respect to AND-EXOR logic, the
proposed method yielded power savings to the tune of 31.88%, while
in comparison with AND-OR-EXOR level networks; average power
savings of 33.23% was obtained.
Abstract: We present a novel scheme to evaluate sinusoidal functions with low complexity and high precision using cubic spline interpolation. To this end, two different approaches are proposed to find the interpolating polynomial of sin(x) within the range [- π , π]. The first one deals with only a single data point while the other with two to keep the realization cost as low as possible. An approximation error optimization technique for cubic spline interpolation is introduced next and is shown to increase the interpolator accuracy without increasing complexity of the associated hardware. The architectures for the proposed approaches are also developed, which exhibit flexibility of implementation with low power requirement.
Abstract: Ultra-low-power (ULP) circuits have received
widespread attention due to the rapid growth of biomedical
applications and Battery-less Electronics. Subthreshold region of
transistor operation is used in ULP circuits. Major research challenge
in the subthreshold operating region is to extract the ULP benefits
with minimal degradation in speed and robustness. Process, Voltage
and Temperature (PVT) variations significantly affect the
performance of subthreshold circuits. Designed performance
parameters of ULP circuits may vary largely due to temperature
variations. Hence, this paper investigates the effect of temperature
variation on device and circuit performance parameters at different
biasing voltages in the subthreshold region. Simulation results clearly
demonstrate that in deep subthreshold and near threshold voltage
regions, performance parameters are significantly affected whereas in
moderate subthreshold region, subthreshold circuits are more
immune to temperature variations. This establishes that moderate
subthreshold region is ideal for temperature immune circuits.
Abstract: This paper describes a novel monitoring scheme to
minimize total active power in digital circuits depend on the demand
frequency, by adjusting automatically both supply voltage and
threshold voltages based on circuit operating conditions such as
temperature, process variations, and desirable frequency. The delay
monitoring results, will be control and apply so as to be maintained at
the minimum value at which the chip is able to operate for a given
clock frequency. Design details of power monitor are examined using
simulation framework in 32nm BTPM model CMOS process.
Experimental results show the overhead of proposed circuit in terms
of its power consumption is about 40 μW for 32nm technology;
moreover the results show that our proposed circuit design is not far
sensitive to the temperature variations and also process variations.
Besides, uses the simple blocks which offer good sensitivity, high
speed, the continuously feedback loop. This design provides up to
40% reduction in power consumption in active mode.
Abstract: Bluetooth is a personal wireless communication
technology and is being applied in many scenarios. It is an emerging
standard for short range, low cost, low power wireless access
technology. Current existing MAC (Medium Access Control)
scheduling schemes only provide best-effort service for all masterslave
connections. It is very challenging to provide QoS (Quality of
Service) support for different connections due to the feature of
Master Driven TDD (Time Division Duplex). However, there is no
solution available to support both delay and bandwidth guarantees
required by real time applications. This paper addresses the issue of
how to enhance QoS support in a Bluetooth piconet. The Bluetooth
specification proposes a Round Robin scheduler as possible solution
for scheduling the transmissions in a Bluetooth Piconet. We propose
an algorithm which will reduce the bandwidth waste and enhance the
efficiency of network. We define token counters to estimate traffic of
real-time slaves. To increase bandwidth utilization, a back-off
mechanism is then presented for best-effort slaves to decrease the
frequency of polling idle slaves. Simulation results demonstrate that
our scheme achieves better performance over the Round Robin
scheduling.
Abstract: The importance of low power consumption is widely
acknowledged due to the increasing use of portable devices, which
require minimizing the consumption of energy. Energy dissipation is
heavily dependent on the software used in the system. Applying
design patterns in object-oriented designs is a common practice
nowadays. In this paper we analyze six design patterns and explore
the effect of them on energy consumption and performance.
Abstract: This paper introduces an adiabatic register file based
on two-phase CPAL (Complementary Pass-Transistor Adiabatic
Logic circuits) with power-gating scheme, which can operate on a
single-phase power clock. A 32×32 single-phase adiabatic register file
with power-gating scheme has been implemented with TSMC 0.18μm
CMOS technology. All the circuits except for the storage cells employ
two-phase CPAL circuits, and the storage cell is based on the
conventional memory one. The two-phase non-overlap power-clock
generator with power-gating scheme is used to supply the proposed
adiabatic register file. Full-custom layouts are drawn. The energy and
functional simulations have been performed using the net-list
extracted from their layouts. Compared with the traditional static
CMOS register file, HSPICE simulations show that the proposed
adiabatic register file can work very well, and it attains about 73%
energy savings at 100 MHz.
Abstract: In the past many uneconomic solutions for limitation
and interruption of short-circuit currents in low power applications
have been introduced, especially polymer switch based on the
positive temperature coefficient of resistance (PCTR) concept.
However there are many limitations in the active material, which
consists of conductive fillers. This paper presents a significantly
improved and simplified approach that replaces the existing current
limiters with faster switching elements. Its elegance lies in the
remarkable simplicity and low-cost processes of producing the device
using polyaniline (PANI) doped with methane-sulfonic acid (MSA).
Samples characterized as lying in the metallic and critical regimes of
metal insulator transition have been studied by means of electrical
performance in the voltage range from 1V to 5 V under different
environmental conditions. Moisture presence is shown to increase the
resistivity and also improved its current limiting performance.
Additionally, the device has also been studied for electrical resistivity
in the temperature range 77 K-300 K. The temperature dependence of
the electrical conductivity gives evidence for a transport mechanism
based on variable range hopping in three dimensions.
Abstract: The designing of charge pump with high gain Op-
Amp is a challenging task for getting faithful response .Design of
high performance phase locked loop require ,a design of high
performance charge pump .We have designed a operational amplifier
for reducing the error caused by high speed glitch in a transistor and
mismatch currents . A separate Op-Amp has designed in 180 nm
CMOS technology by CADENCE VIRTUOSO tool. This paper
describes the design of high performance charge pump for GHz
CMOS PLL targeting orthogonal frequency division multiplexing
(OFDM) application. A high speed low power consumption Op-Amp
with more than 500 MHz bandwidth has designed for increasing the
speed of charge pump in Phase locked loop.
Abstract: In this paper, an analysis is presented, which
demonstrates the effect pre-logic factoring could have on an
automated combinational logic synthesis process succeeding it. The
impact of pre-logic factoring for some arbitrary combinatorial
circuits synthesized within a FPGA based logic design environment
has been analyzed previously. This paper explores a similar effect,
but with the non-regenerative logic synthesized using elements of a
commercial standard cell library. On an overall basis, the results
obtained pertaining to the analysis on a variety of MCNC/IWLS
combinational logic benchmark circuits indicate that pre-logic
factoring has the potential to facilitate simultaneous power, delay and
area optimized synthesis solutions in many cases.
Abstract: Memristor is also known as the fourth fundamental
passive circuit element. When current flows in one direction through
the device, the electrical resistance increases and when current flows
in the opposite direction, the resistance decreases. When the current
is stopped, the component retains the last resistance that it had, and
when the flow of charge starts again, the resistance of the circuit will
be what it was when it was last active. It behaves as a nonlinear
resistor with memory. Recently memristors have generated wide
research interest and have found many applications. In this paper we
survey the various applications of memristors which include non
volatile memory, nanoelectronic memories, computer logic,
neuromorphic computer architectures low power remote sensing
applications, crossbar latches as transistor replacements, analog
computations and switches.
Abstract: The purpose of this investigation is to relate the rain
power and the overland flow power to soil erodibility to assess the
effects of both parameters on soil erosion using variable rainfall
intensity on remoulded agricultural soil. Six rainfall intensities were
used to simulate the natural rainfall and are as follows: 12.4mm/h,
20.3mm/h, 28.6mm/h, 52mm/h, 73.5mm/h and 103mm/h. The results
have shown that the relationship between overland flow power and
rain power is best represented by a linear function (R2=0.99). As
regards the relationships between soil erodibility factor and rain and
overland flow powers, the evolution of both parameters with the
erodibility factor follow a polynomial function with high coefficient
of determination. From their coefficients of determination (R2=0.95)
for rain power and (R2=0.96) for overland flow power, we can
conclude that the flow has more power to detach particles than rain.
This could be explained by the fact that the presence of particles,
already detached by rain and transported by the flow, give the flow
more weight and then contribute to the detachment of particles by
collision.
Abstract: In this paper, the problem of reducing switching
activity in on-chip buses at the stage of high-level synthesis is
considered, and a high-level low power bus binding based on dynamic
bit reordering is proposed. Whereas conventional methods use a fixed
bit ordering between variables within a bus, the proposed method
switches a bit ordering dynamically to obtain a switching activity
reduction. As a result, the proposed method finds a binding solution
with a smaller value of total switching activity (TSA). Experimental
result shows that the proposed method obtains a binding solution
having 12.0-34.9% smaller TSA compared with the conventional
methods.
Abstract: This paper proposes a low power SRAM based on
five transistor SRAM cell. Proposed SRAM uses novel word-line
decoding such that, during read/write operation, only selected cell
connected to bit-line whereas, in conventional SRAM (CV-SRAM),
all cells in selected row connected to their bit-lines, which in turn
develops differential voltages across all bit-lines, and this makes
energy consumption on unselected bit-lines. In proposed SRAM
memory array divided into two halves and this causes data-line
capacitance to reduce. Also proposed SRAM uses one bit-line and
thus has lower bit-line leakage compared to CV-SRAM.
Furthermore, the proposed SRAM incurs no area overhead, and has
comparable read/write performance versus the CV-SRAM.
Simulation results in standard 0.25μm CMOS technology shows in
worst case proposed SRAM has 80% smaller dynamic energy
consumption in each cycle compared to CV-SRAM. Besides, energy
consumption in each cycle of proposed SRAM and CV-SRAM
investigated analytically, the results of which are in good agreement
with the simulation results.
Abstract: In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.
Abstract: Wireless Sensor Networks (WSNs) are wireless
networks consisting of number of tiny, low cost and low power
sensor nodes to monitor various physical phenomena like
temperature, pressure, vibration, landslide detection, presence of any
object, etc. The major limitation in these networks is the use of nonrechargeable
battery having limited power supply. The main cause of
energy consumption WSN is communication subsystem. This paper
presents an efficient grid formation/clustering strategy known as Grid
based level Clustering and Aggregation of Data (GCAD). The
proposed clustering strategy is simple and scalable that uses low duty
cycle approach to keep non-CH nodes into sleep mode thus reducing
energy consumption. Simulation results demonstrate that our
proposed GCAD protocol performs better in various performance
metrics.