Abstract: Recursive combination of an algorithm based on Karatsuba multiplication is exploited to design a generalized transpose and parallel Finite Impulse Response (FIR) Filter. Mid-range Karatsuba multiplication and Carry Save adder based on Karatsuba multiplication reduce time complexity for higher order multiplication implemented up to n-bit. As a result, we design modified N-tap Transpose and Parallel Symmetric FIR Filter Structure using Karatsuba algorithm. The mathematical formulation of the FFA Filter is derived. The proposed architecture involves significantly less area delay product (APD) then the existing block implementation. By adopting retiming technique, hardware cost is reduced further. The filter architecture is designed by using 90 nm technology library and is implemented by using cadence EDA Tool. The synthesized result shows better performance for different word length and block size. The design achieves switching activity reduction and low power consumption by applying with and without retiming for different combination of the circuit. The proposed structure achieves more than a half of the power reduction by adopting with and without retiming techniques compared to the earlier design structure. As a proof of the concept for block size 16 and filter length 64 for CKA method, it achieves a 51% as well as 70% less power by applying retiming technique, and for CSA method it achieves a 57% as well as 77% less power by applying retiming technique compared to the previously proposed design.
Abstract: The growing popularity of solid state thermoelectric
devices in cooling applications has sparked an increasing diversity of
thermoelectric coolers (TECs) on the market, commonly known as
“Peltier modules”. They can also be used as generators, converting
a temperature difference into electric power, and opportunities are
plentiful to make use of these devices as thermoelectric generators
(TEGs) to supply energy to low power, autonomous embedded
electronic applications. Their adoption as energy harvesters in this
new domain of usage is obstructed by the complex thermoelectric
models commonly associated with TEGs. Low cost TECs for the
consumer market lack the required parameters to use the models
because they are not intended for this mode of operation, thereby
urging an alternative method to obtain electric power estimations
in specific operating conditions. The design of the test setup
implemented in this paper is specifically targeted at benchmarking
commercial, off-the-shelf TECs for use as energy harvesters in
domestic environments: applications with limited temperature
differences and space available. The usefulness is demonstrated by
testing and comparing single and multi stage TECs with different
sizes. The effect of a boost converter stage on the thermoelectric
end-to-end efficiency is also discussed.
Abstract: In this paper, an embedded frequency modulation
(FM) transmission control software (SW) for a low power battery
system is designed and implemented. The simultaneous translation
systems for various languages are needed as so many international
conferences and festivals are held in world wide. Especially in
portable transmitting and receiving systems, the ability of long
operation life is used for a measure of value. This paper proposes
an embedded FM transmission control SW for low power battery
system and shows the results of the SW implemented on a portable
FM transmission system.
Abstract: In sub micrometer technology, the aging phenomenon starts to have a significant impact on the reliability of integrated circuits by bringing performance degradation. For that reason, it is important to have a capability to evaluate the aging effects accurately. This paper presents an accurate aging measurement approach based on phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuit. The architecture is rejecting the circuit self-aging effect from the characteristics of PLL, which is generating the frequency without any aging phenomena affects. The aging monitor is implemented in low power 32 nm CMOS technology, and occupies a pretty small area. Aging simulation results show that the proposed aging measurement circuit improves accuracy by about 2.8% at high temperature and 19.6% at high voltage.
Abstract: Renowned offshore organizations are drifting towards collaborative exertion to win and implement international projects for business gains. However, devoid of financial constraints, with the availability of skilled professionals, and despite improved project management practices through state-of-the-art tools and techniques, project delays have become a norm these days. This situation calls for exploring the factor(s) affecting the bonding between project management performance and project success. In the context of the well-known 3M’s of project management (that is, manpower, machinery, and materials), machinery and materials are dependent upon manpower. Because the body of knowledge inveterate on the influence of national culture on men, hence, the realization of the impact on the link between project management performance and project success need to be investigated in detail to arrive at the possible cause(s) of project delays. This research initiative was, therefore, undertaken to fill the research gap. The unit of analysis for the proposed research excretion was the individuals who had worked on skyscraper construction projects. In reverent studies, project management is best described using construction examples. It is due to this reason that the project oriented city of Dubai was chosen to reconnoiter on causes of project delays. A structured questionnaire survey was disseminated online with the courtesy of the Project Management Institute local chapter to carry out the cross-sectional study. The Construction Industry Institute, Austin, of the United States of America along with 23 high-rise builders in Dubai were also contacted by email requesting for their contribution to the study and providing them with the online link to the survey questionnaire. The reliability of the instrument was warranted using Cronbach’s alpha coefficient of 0.70. The appropriateness of sampling adequacy and homogeneity in variance was ensured by keeping Kaiser–Meyer–Olkin (KMO) and Bartlett’s test of sphericity in the range ≥ 0.60 and < 0.05, respectively. Factor analysis was used to verify construct validity. During exploratory factor analysis, all items were loaded using a threshold of 0.4. Four hundred and seventeen respondents, including members from top management, project managers, and project staff, contributed to the study. The link between project management performance and project success was significant at 0.01 level (2-tailed), and 0.05 level (2-tailed) for Pearson’s correlation. Before initiating the moderator analysis test for linearity, multicollinearity, outliers, leverage points and influential cases, test for homoscedasticity and normality were carried out which are prerequisites for conducting moderator review. The moderator analysis, using a macro named PROCESS, was performed to verify the hypothesis that national culture has an influence on the said link. The empirical findings, when compared with Hofstede's results, showed high power distance as the cause of construction project delays in Dubai. The research outcome calls for the project sponsors and top management to reshape their project management strategy and allow for low power distance between management and project personnel for timely completion of projects.
Abstract: Air jet weaving is the most productive, but also the most energy consuming weaving method. Increasing energy costs and environmental impact are constantly a challenge for the manufacturers of weaving machines. Current technological developments concern with low energy costs, low environmental impact, high productivity, and constant product quality. The high degree of energy consumption of the method can be ascribed to the high need of compressed air. An energy efficiency method is applied to the air jet weaving technology. Such method identifies and classifies the main relevant energy consumers and processes from the exergy point of view and it leads to the identification of energy efficiency potentials during the weft insertion process. Starting from the design phase, energy efficiency is considered as the central requirement to be satisfied. The initial phase of the method consists of an analysis of the state of the art of the main weft insertion components in order to point out a prioritization of the high demanding energy components and processes. The identified major components are investigated to reduce the high demand of energy of the weft insertion process. During the interaction of the flow field coming from the relay nozzles within the profiled reed, only a minor part of the stream is really accelerating the weft yarn, hence resulting in large energy inefficiency. Different tools such as FEM analysis, CFD simulation models and experimental analysis are used in order to design a more energy efficient design of the involved components in the filling insertion. A different concept for the metal strip of the profiled reed is developed. The developed metal strip allows a reduction of the machine energy consumption. Based on a parametric and aerodynamic study, the designed reed transmits higher values of the flow power to the filling yarn. The innovative reed fulfills both the requirement of raising energy efficiency and the compliance with the weaving constraints.
Abstract: Wireless sensor networks (WSNs), are constantly in demand to process information more rapidly with less energy and area cost. Presently, processor based solutions have difficult to achieve high processing speed with low-power consumption. This paper presents a simple and accurate data processing scheme for low power wireless sensor node, based on reduced number of processing element (PE). The presented model provides a simple recursive structure (SRS) to process the sampled data in the wireless sensor environment and to reduce the power consumption in wireless sensor node. Based on this model, to process the incoming samples and produce a smaller amount of data sufficient to reconstruct the original signal. The ModelSim simulator used to simulate SRS structure. Functional simulation is carried out for the validation of the presented architecture. Xilinx Power Estimator (XPE) tool is used to measure the power consumption. The experimental results show the average power consumption of 91 mW; this is 42% improvement compared to the folded tree architecture.
Abstract: Power dissipation increases exponentially during test mode as compared to normal operation of the circuit. In extreme cases, test power is more than twice the power consumed during normal operation mode. Test vector generation scheme is key component in deciding the power hungriness of a circuit during testing. Test vector count and consequent leakage current are functions of test vector generation scheme. Fault based test vector count optimization has been presented in this work. It helps in reducing test vector count and the leakage current. In the presented scheme, test vectors have been reduced by extracting essential child vectors. The scheme has been tested experimentally using stuck at fault models and results ensure the reduction in test vector count.
Abstract: It is necessary to realize new biomedical wireless communication systems which send the signals collected from various bio sensors located at human body in order to monitor our health. Also, it should seamlessly connect to the existing wireless communication systems. A 5.8 GHz ISM band low power RF front-end receiver for a biomedical wireless communication system is implemented using a 0.5 µm SiGe BiCMOS process. To achieve low power RF front-end, the current optimization technique for selecting device size is utilized. The implemented low noise amplifier (LNA) shows a power gain of 9.8 dB, a noise figure (NF) of below 1.75 dB, and an IIP3 of higher than 7.5 dBm while current consumption is only 6 mA at supply voltage of 2.5 V. Also, the performance of a down-conversion mixer is measured as a conversion gain of 11 dB and SSB NF of 10 dB.
Abstract: Small scale hydropower used to play a very important role in the provision of energy to urban and rural areas of South Africa. The national electricity grid, however, expanded and offered cheap, coal generated electricity and a large number of hydropower systems were decommissioned. Unfortunately, large numbers of households and communities will not be connected to the national electricity grid for the foreseeable future due to high cost of transmission and distribution systems to remote communities due to the relatively low electricity demand within rural communities and the allocation of current expenditure on upgrading and constructing of new coal fired power stations. This necessitates the development of feasible alternative power generation technologies. A feasibility and implementation model was developed to assist in designing and financially evaluating small-scale hydropower (SSHP) plants. Several sites were identified using the model. The SSHP plants were designed for the selected sites and the designs for the different selected sites were priced using pricing models (civil, mechanical and electrical aspects). Following feasibility studies done on the designed and priced SSHP plants, a feasibility analysis was done and a design chart developed for future similar potential SSHP plant projects. The methodology followed in conducting the feasibility analysis for other potential sites consisted of developing cost and income/saving formulae, developing net present value (NPV) formulae, Capital Cost Comparison Ratio (CCCR) and levelised cost formulae for SSHP projects for the different types of plant installations. It included setting up a model for the development of a design chart for a SSHP, calculating the NPV, CCCR and levelised cost for the different scenarios within the model by varying different parameters within the developed formulae, setting up the design chart for the different scenarios within the model and analyzing and interpreting results. From the interpretation of the develop design charts for feasible SSHP in can be seen that turbine and distribution line cost are the major influences on the cost and feasibility of SSHP. High head, short transmission line and islanded mini-grid SSHP installations are the most feasible and that the levelised cost of SSHP is high for low power generation sites. The main conclusion from the study is that the levelised cost of SSHP projects indicate that the cost of SSHP for low energy generation is high compared to the levelised cost of grid connected electricity supply; however, the remoteness of SSHP for rural electrification and the cost of infrastructure to connect remote rural communities to the local or national electricity grid provides a low CCCR and renders SSHP for rural electrification feasible on this basis.
Abstract: In this paper, the effect of the injected current and temperature into the output power of the laser diode module operating at 808nm were applied, studied and discussed. Low power diode laser was employed as a source. The experimental results were demonstrated and then the output power of laser diode module operating at 808nm was clearly changed by the thermal temperature and injected current. The output power increases by the increasing the injected current and temperature. We also showed that the increasing of the injected current results rising in heat, which also, results into decreasing of the laser diode output power during the highest temperature as well. The best ranges of characteristics made by diode module operating at 808nm were carefully handled and determined.
Abstract: Matching an embedded electronic application with a
cantilever vibration energy harvester remains a difficult endeavour
due to the large number of factors influencing the output power.
In the presented work, complementary balanced energy harvester
parametrization is used as a methodology for simplification of
harvester integration in electronic applications. This is achieved
by a dual approach consisting of an adaptation of the general
parametrization methodology in conjunction with a straight forward
harvester benchmarking strategy. For this purpose, the design and
implementation of a suitable user friendly cantilever energy harvester
benchmarking platform is discussed. Its effectiveness is demonstrated
by applying the methodology to a commercially available Mide
V21BL vibration energy harvester, with excitation amplitude and
frequency as variables.
Abstract: Ubiquity of natural disasters during last few decades
have risen serious questions towards the prediction of such events
and human safety. Every disaster regardless its proportion has a
precursor which is manifested as a disruption of some environmental
parameter such as temperature, humidity, pressure, vibrations and
etc. In order to anticipate and monitor those changes, in this paper
we propose an overall system for disaster prediction and monitoring,
based on wireless sensor network (WSN). Furthermore, we introduce
a modified and simplified WSN routing protocol built on the top
of the trickle routing algorithm. Routing algorithm was deployed
using the bluetooth low energy protocol in order to achieve low
power consumption. Performance of the WSN network was analyzed
using a real life system implementation. Estimates of the WSN
parameters such as battery life time, network size and packet delay are
determined. Based on the performance of the WSN network, proposed
system can be utilized for disaster monitoring and prediction due to
its low power profile and mesh routing feature.
Abstract: In this paper, a low voltage high performance current mirror is presented. Its most important specifications, which are improved in this work, are analyzed and formulated proving that it has such outstanding merits as: Very low input resistance of 26mΩ, very wide current dynamic range of 8 decades from 10pA to 1mA (160dB) together with an extremely low current copy error of less than 0.6ppm, and very low input and output voltages. Furthermore, the proposed current mirror bandwidth is 944MHz utilizing very low power consumption (267μW) and transistors count. HSPICE simulation results are performed using TSMC 0.18μm CMOS technology utilizing 1.8V single power supply, confirming the theoretically proved outstanding performance of the proposed current mirror. Monte Carlo simulation of its most important parameter is also examined showing its sufficiently resistance against technology process variations.
Abstract: The main issue in designing a wireless sensor network
(WSN) is the finding of a proper routing protocol that complies with
the several requirements of high reliability, short latency, scalability,
low power consumption, and many others. This paper proposes a
novel routing algorithm that complies with these design
requirements. The new routing protocol divides the WSN into several subnetworks
and each sub-network is divided into several clusters. This
division is designed to reduce the number of radio transmission and
hence decreases the power consumption. The network division may
be changed dynamically to adapt with the network changes and
allows the realization of the design requirements.
Abstract: In internet of things (IoT) system, the communication
scheme with reliability and low power is required to connect a
terminal. Cooperative communication can achieve reliability and
lower power than multiple-input multiple-output (MIMO) system.
Cooperative communication increases the reliability with low
power, but decreases a throughput. It has a weak point that the
communication throughput is decreased. In this paper, a novel scheme
is proposed to increase the communication throughput. The novel
scheme is a transmission structure that increases transmission rate.
A decoding scheme according to the novel transmission structure is
proposed. Simulation results show that the proposed scheme increases
the throughput without bit error rate (BER) performance degradation.
Abstract: This paper presents the design and fabrication of a
novel piezoelectric actuator for a gas micro pump with check valve
having the advantages of miniature size, light weight and low power
consumption. The micro pump is designed to have eight major
components, namely a stainless steel upper cover layer, a piezoelectric
actuator, a stainless steel diaphragm, a PDMS chamber layer, two
stainless steel channel layers with two valve seats, a PDMS check
valve layer with two cantilever-type check valves and an acrylic
substrate. A prototype of the gas micro pump, with a size of 52 mm ×
50 mm × 5.0 mm, is fabricated by precise manufacturing. This device
is designed to pump gases with the capability of performing the
self-priming and bubble-tolerant work mode by maximizing the stroke
volume of the membrane as well as the compression ratio via
minimization of the dead volume of the micro pump chamber and
channel. By experiment apparatus setup, we can get the real-time
values of the flow rate of micro pump and the displacement of the
piezoelectric actuator, simultaneously. The gas micro pump obtained
higher output performance under the sinusoidal waveform of 250 Vpp.
The micro pump achieved the maximum pumping rates of 1185
ml/min and back pressure of 7.14 kPa at the corresponding frequency
of 120 and 50 Hz.
Abstract: A novel design technique employing CMOS Current
Feedback Operational Amplifier (CFOA) is presented. The feature of
consumption very low power in designing pseudo-OTA is used to
decreasing the total power consumption of the proposed CFOA. This
design approach applies pseudo-OTA as input stage cascaded with
buffer stage. Moreover, the DC input offset voltage and harmonic
distortion (HD) of the proposed CFOA are very low values compared
with the conventional CMOS CFOA due to the symmetrical input
stage. P-Spice simulation results are obtained using 0.18μm MIETEC
CMOS process parameters and supply voltage of ±1.2V, 50μA
biasing current. The p-spice simulation shows excellent improvement
of the proposed CFOA over existing CMOS CFOA. Some of these
performance parameters, for example, are DC gain of 62. dB, openloop
gain bandwidth product of 108 MHz, slew rate (SR+) of
+71.2V/μS, THD of -63dB and DC consumption power (PC) of
2mW.
Abstract: This research paper presents highly optimized barrel
shifter at 22nm Hi K metal gate strained Si technology node. This
barrel shifter is having a unique combination of static and dynamic
body bias which gives lowest power delay product. This power delay
product is compared with the same circuit at same technology node
with static forward biasing at ‘supply/2’ and also with normal reverse
substrate biasing and still found to be the lowest. The power delay
product of this barrel sifter is .39362X10-17J and is lowered by
approximately 78% to reference proposed barrel shifter at 32nm bulk
CMOS technology. Power delay product of barrel shifter at 22nm Hi
K Metal gate technology with normal reverse substrate bias is
2.97186933X10-17J and can be compared with this design’s PDP of
.39362X10-17J. This design uses both static and dynamic substrate
biasing and also has approximately 96% lower power delay product
compared to only forward body biased at half of supply voltage. The
NMOS model used are predictive technology models of Arizona state
university and the simulations to be carried out using HSPICE
simulator.
Abstract: This paper proposes techniques like MT CMOS,
POWER GATING, DUAL STACK, GALEOR and LECTOR to
reduce the leakage power. A Full Adder has been designed using
these techniques and power dissipation is calculated and is compared
with general CMOS logic of Full Adder.
Simulation results show the validity of the proposed techniques is
effective to save power dissipation and to increase the speed of
operation of the circuits to a large extent.