Abstract: With rapid technology scaling, the proportion of the
static power consumption catches up with dynamic power
consumption gradually. To decrease leakage consumption is
becoming more and more important in low-power design. This paper
presents a power-gating scheme for P-DTGAL (p-type dual
transmission gate adiabatic logic) circuits to reduce leakage power
dissipations under deep submicron process. The energy dissipations of
P-DTGAL circuits with power-gating scheme are investigated in
different processes, frequencies and active ratios. BSIM4 model is
adopted to reflect the characteristics of the leakage currents. HSPICE
simulations show that the leakage loss is greatly reduced by using the
P-DTGAL with power-gating techniques.
Abstract: For higher order multiplications, a huge number of
adders or compressors are to be used to perform the partial product
addition. We have reduced the number of adders by introducing
special kind of adders that are capable to add five/six/seven bits per
decade. These adders are called compressors. Binary counter
property has been merged with the compressor property to develop
high order compressors. Uses of these compressors permit the
reduction of the vertical critical paths. A 16×16 bit multiplier has
been developed using these compressors. These compressors make
the multipliers faster as compared to the conventional design that
have been used 4-2 compressors and 3-2 compressors.
Abstract: The flash memory has many advantages such as low power consumption, strong shock resistance, fast I/O and non-volatility. And it is increasingly used in the mobile storage device. The YAFFS, one of the NAND flash file system, is widely used in the embedded device. However, the existing YAFFS takes long time to mount the file system because it scans whole spare areas in all pages of NAND flash memory. In order to solve this problem, we propose a new content-based flash file system using a mounting time reduction technique. The proposed method only scans partial spare areas of some special pages by using content-based block management. The experimental results show that the proposed method reduces the average mounting time by 87.2% comparing with JFFS2 and 69.9% comparing with YAFFS.
Abstract: with increasing circuits- complexity and demand to
use portable devices, power consumption is one of the most
important parameters these days. Full adders are the basic block of
many circuits. Therefore reducing power consumption in full adders
is very important in low power circuits. One of the most powerconsuming
modules in full adders is XOR/XNOR circuit. This paper
presents two new full adders based on two new logic approaches. The
proposed logic approaches use one XOR or XNOR gate to implement
a full adder cell. Therefore, delay and power will be decreased. Using
two new approaches and two XOR and XNOR gates, two new full
adders have been implemented in this paper. Simulations are carried
out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage.
The results show that the ten-transistors proposed full adder has 12%
less power consumption and is 5% faster in comparison to MB12T
full adder. 9T is more efficient in area and is 24% better than similar
10T full adder in term of power consumption. The main drawback of
the proposed circuits is output threshold loss problem.
Abstract: An approach and its implementation in 0.18 m CMOS process of the multichannel ASIC for capacitive (up to 30 pF) sensors are described in the paper. The main design aim was to study an analog data-driven architecture. The design was done for an analog derandomizing function of the 128 to 16 structure. That means that the ASIC structure should provide a parallel front-end readout of 128 input analog sensor signals and after the corresponding fast commutation with appropriate arbitration logic their processing by means of 16 output chains, including analog-to-digital conversion. The principal feature of the ASIC is a low power consumption within 2 mW/channel (including a 9-bit 20Ms/s ADC) at a maximum average channel hit rate not less than 150 kHz.
Abstract: Considering payload, reliability, security and operational lifetime as major constraints in transmission of images we put forward in this paper a steganographic technique implemented at the physical layer. We suggest transmission of Halftoned images (payload constraint) in wireless sensor networks to reduce the amount of transmitted data. For low power and interference limited applications Turbo codes provide suitable reliability. Ensuring security is one of the highest priorities in many sensor networks. The Turbo Code structure apart from providing forward error correction can be utilized to provide for encryption. We first consider the Halftoned image and then the method of embedding a block of data (called secret) in this Halftoned image during the turbo encoding process is presented. The small modifications required at the turbo decoder end to extract the embedded data are presented next. The implementation complexity and the degradation of the BER (bit error rate) in the Turbo based stego system are analyzed. Using some of the entropy based crypt analytic techniques we show that the strength of our Turbo based stego system approaches that found in the OTPs (one time pad).
Abstract: In this paper, a alternative structure method for
continuous time sigma delta modulator is presented. In this
modulator for implementation of integrators in loop filter second
generation current conveyors are employed. The modulator is
designed in CMOS technology and features low power consumption
(65db),
and with 180khZ bandwidth. Simulation results confirm that this
design is suitable for data converters.
Abstract: In Image processing the Image compression can improve
the performance of the digital systems by reducing the cost and
time in image storage and transmission without significant reduction
of the Image quality. This paper describes hardware architecture of
low complexity Discrete Cosine Transform (DCT) architecture for
image compression[6]. In this DCT architecture, common computations
are identified and shared to remove redundant computations
in DCT matrix operation. Vector processing is a method used for
implementation of DCT. This reduction in computational complexity
of 2D DCT reduces power consumption. The 2D DCT is performed
on 8x8 matrix using two 1-Dimensional Discrete cosine transform
blocks and a transposition memory [7]. Inverse discrete cosine
transform (IDCT) is performed to obtain the image matrix and
reconstruct the original image. The proposed image compression
algorithm is comprehended using MATLAB code. The VLSI design
of the architecture is implemented Using Verilog HDL. The proposed
hardware architecture for image compression employing DCT was
synthesized using RTL complier and it was mapped using 180nm
standard cells. . The Simulation is done using Modelsim. The
simulation results from MATLAB and Verilog HDL are compared.
Detailed analysis for power and area was done using RTL compiler
from CADENCE. Power consumption of DCT core is reduced to
1.027mW with minimum area[1].
Abstract: This paper describes the experimental efficiency of a
compact organic Rankine cycle (ORC) system with a compact
rotary-vane-type expander. The compact ORC system can be used for
power generation from low-temperature heat sources such as waste
heat from various small-scale heat engines, fuel cells, electric devices,
and solar thermal energy. The purpose of this study is to develop an
ORC system with a low power output of less than 1 kW with a hot
temperature source ranging from 60°C to 100°C and a cold
temperature source ranging from 10°C to 30°C. The power output of
the system is rather less due to limited heat efficiency. Therefore, the
system should have an economically optimal efficiency. In order to
realize such a system, an efficient and low-cost expander is
indispensable. An experimental ORC system was developed using the
rotary-vane-type expander which is one of possible candidates of the
expander. The experimental results revealed the expander
performance for various rotation speeds, expander efficiencies, and
thermal efficiencies. Approximately 30 W of expander power output
with 48% expander efficiency and 4% thermal efficiency with a
temperature difference between the hot and cold sources of 80°C was
achieved.
Abstract: In this paper, an ultra low power and low jitter 12bit
CMOS digitally controlled oscillator (DCO) design is presented.
Based on a ring oscillator implemented with low power Schmitt
trigger based inverters. Simulation of the proposed DCO using 32nm
CMOS Predictive Transistor Model (PTM) achieves controllable
frequency range of 550MHz~830MHz with a wide linearity and high
resolution. Monte Carlo simulation demonstrates that the time-period
jitter due to random power supply fluctuation is under 31ps and the
power consumption is 0.5677mW at 750MHz with 1.2V power
supply and 0.53-ps resolution. The proposed DCO has a good
robustness to voltage and temperature variations and better linearity
comparing to the conventional design.
Abstract: In this paper, the implementation of low power,
high throughput convolutional filters for the one dimensional
Discrete Wavelet Transform and its inverse are presented. The
analysis filters have already been used for the implementation of a
high performance DWT encoder [15] with minimum memory
requirements for the JPEG 2000 standard. This paper presents the
design techniques and the implementation of the convolutional filters
included in the JPEG2000 standard for the forward and inverse DWT
for achieving low-power operation, high performance and reduced
memory accesses. Moreover, they have the ability of performing
progressive computations so as to minimize the buffering between
the decomposition and reconstruction phases. The experimental
results illustrate the filters- low power high throughput characteristics
as well as their memory efficient operation.
Abstract: This paper deals with a power-conscious ANDEXOR- Inverter type logic implementation for a complex class of Boolean functions, namely Achilles- heel functions. Different variants of the above function class have been considered viz. positive, negative and pure horn for analysis and simulation purposes. The proposed realization is compared with the decomposed implementation corresponding to an existing standard AND-EXOR logic minimizer; both result in Boolean networks with good testability attribute. It could be noted that an AND-OR-EXOR type logic network does not exist for the positive phase of this unique class of logic function. Experimental results report significant savings in all the power consumption components for designs based on standard cells pertaining to a 130nm UMC CMOS process The simulations have been extended to validate the savings across all three library corners (typical, best and worst case specifications).
Abstract: A healthcare monitoring system is presented in this
paper. This system is based on ultra-low power sensor nodes and a
personal server, which is based on hardware and software extensions
to a Personal Digital Assistant (PDA)/Smartphone. The sensor node
collects data from the body of a patient and sends it to the personal
server where the data is processed, displayed and made ready to be
sent to a healthcare network, if necessary. The personal server
consists of a compact low power receiver module and equipped with
a Smartphone software. The receiver module takes less than 30 × 30
mm board size and consumes approximately 25 mA in active mode.
Abstract: A conventional binding method for low power in a
high-level synthesis mainly focuses on finding an optimal binding for
an assumed input data, and obtains only one binding table. In this
paper, we show that a binding method which uses multiple binding
tables gets better solution compared with the conventional methods
which use a single binding table, and propose a dynamic bus binding
scheme for low power using multiple binding tables. The proposed
method finds multiple binding tables for the proper partitions of an
input data, and switches binding tables dynamically to produce the
minimum total switching activity. Experimental result shows that the
proposed method obtains a binding solution having 12.6-28.9%
smaller total switching activity compared with the conventional
methods.
Abstract: The more recent satellite projects/programs makes
extensive usage of real – time embedded systems. 16 bit processors
which meet the Mil-Std-1750 standard architecture have been used in
on-board systems. Most of the Space Applications have been written
in ADA. From a futuristic point of view, 32 bit/ 64 bit processors are
needed in the area of spacecraft computing and therefore an effort is
desirable in the study and survey of 64 bit architectures for space
applications. This will also result in significant technology
development in terms of VLSI and software tools for ADA (as the
legacy code is in ADA).
There are several basic requirements for a special processor for
this purpose. They include Radiation Hardened (RadHard) devices,
very low power dissipation, compatibility with existing operational
systems, scalable architectures for higher computational needs,
reliability, higher memory and I/O bandwidth, predictability, realtime
operating system and manufacturability of such processors.
Further on, these may include selection of FPGA devices, selection
of EDA tool chains, design flow, partitioning of the design, pin
count, performance evaluation, timing analysis etc.
This project deals with a brief study of 32 and 64 bit processors
readily available in the market and designing/ fabricating a 64 bit
RISC processor named RISC MicroProcessor with added
functionalities of an extended double precision floating point unit
and a 32 bit signal processing unit acting as co-processors. In this
paper, we emphasize the ease and importance of using Open Core
(OpenSparc T1 Verilog RTL) and Open “Source" EDA tools such as
Icarus to develop FPGA based prototypes quickly. Commercial tools
such as Xilinx ISE for Synthesis are also used when appropriate.
Abstract: The effects of ethylene (C2H4) feed position and
O2/C2H4 feed molar ratio on ethylene epoxidation in a parallel
dielectric barrier discharge (DBD) were studied. The results showed
that the ethylene feed position fraction of 0.5 and the feed molar
ratio of O2/C2H4 of 0.2:1 gave the highest EO selectivity of 34.3%
and the highest EO yield of 5.28% with low power consumptions of
2.11×10-16 Ws/molecule of ethylene converted and 6.34×10-16
Ws/molecule of EO produced when the DBD system was operated
under the best conditions: an applied voltage of 19 kV, an input
frequency of 500 Hz and a total feed flow rate of 50 cm3/min. The
separate ethylene feed system provided much higher epoxidation
activity as compared to the mixed feed system which gave EO
selectivity of 15.5%, EO yield of 2.1% and the power consumption of
EO produced of 7.7×10-16 Ws/molecule.
Abstract: Variations in the growth rate constant of the Listeria
monocytogenes bacterial species were determined at 37°C in
irradiated environments and compared to the situation of a nonirradiated
environment. The bacteria cells, contained in a suspension
made of a nutrient solution of Brain Heart Infusion, were made to
grow at different frequency (2.30e2.60 GHz) and power (0e400
mW) values, in a plug flow reactor positioned in the irradiated
environment. Then the reacting suspension was made to pass into a
cylindrical cuvette where its optical density was read every 2.5
minutes at a wavelength of 600 nm. The obtained experimental data
of optical density vs. time allowed the bacterial growth rate constant
to be derived; this was found to be slightly influenced by microwave
power, but not by microwave frequency; in particular, a minimum
value was found for powers in the 50e150 mW field.
Abstract: Fully customized hardware based technology provides high performance and low power consumption by specializing the tasks in hardware but lacks design flexibility since any kind of changes require re-design and re-fabrication. Software based solutions operate with software instructions due to which a great flexibility is achieved from the easy development and maintenance of the software code. But this execution of instructions introduces a high overhead in performance and area consumption. In past few decades the reconfigurable computing domain has been introduced which overcomes the traditional trades-off between flexibility and performance and is able to achieve high performance while maintaining a good flexibility. The dramatic gains in terms of chip performance and design flexibility achieved through the reconfigurable computing systems are greatly dependent on the design of their computational units being integrated with reconfigurable logic resources. The computational unit of any reconfigurable system plays vital role in defining its strength. In this research paper an RFU based computational unit design has been presented using the tightly coupled, multi-threaded reconfigurable cores. The proposed design has been simulated for VLIW based architectures and a high gain in performance has been observed as compared to the conventional computing systems.
Abstract: This paper describes a CMOS four-quadrant
multiplier intended for use in the front-end receiver by utilizing the
square-law characteristic of the MOS transistor in the saturation
region. The circuit is based on 0.35 um CMOS technology simulated
using HSPICE software. The mixer has a third-order inter the power
consumption is 271uW from a single 1.2V power supply. One of the
features of the proposed design is using two MOS transistors
limitation to reduce the supply voltage, which leads to reduce the
power consumption. This technique provides a GHz bandwidth
response and low power consumption.
Abstract: Distributed wireless sensor network consist on several
scattered nodes in a knowledge area. Those sensors have as its only
power supplies a pair of batteries that must let them live up to five
years without substitution. That-s why it is necessary to develop
some power aware algorithms that could save battery lifetime as
much as possible. In this is document, a review of power aware
design for sensor nodes is presented. As example of implementations,
some resources and task management, communication, topology
control and routing protocols are named.