Abstract: Recursive combination of an algorithm based on Karatsuba multiplication is exploited to design a generalized transpose and parallel Finite Impulse Response (FIR) Filter. Mid-range Karatsuba multiplication and Carry Save adder based on Karatsuba multiplication reduce time complexity for higher order multiplication implemented up to n-bit. As a result, we design modified N-tap Transpose and Parallel Symmetric FIR Filter Structure using Karatsuba algorithm. The mathematical formulation of the FFA Filter is derived. The proposed architecture involves significantly less area delay product (APD) then the existing block implementation. By adopting retiming technique, hardware cost is reduced further. The filter architecture is designed by using 90 nm technology library and is implemented by using cadence EDA Tool. The synthesized result shows better performance for different word length and block size. The design achieves switching activity reduction and low power consumption by applying with and without retiming for different combination of the circuit. The proposed structure achieves more than a half of the power reduction by adopting with and without retiming techniques compared to the earlier design structure. As a proof of the concept for block size 16 and filter length 64 for CKA method, it achieves a 51% as well as 70% less power by applying retiming technique, and for CSA method it achieves a 57% as well as 77% less power by applying retiming technique compared to the previously proposed design.
Abstract: In this paper, we address the problem of reducing the
switching activity (SA) in on-chip buses through the use of a bus
binding technique in high-level synthesis. While many binding
techniques to reduce the SA exist, we present yet another technique for
further reducing the switching activity. Our proposed method
combines bus binding and data sequence reordering to explore a wider
solution space. The problem is formulated as a multiple traveling
salesman problem and solved using simulated annealing technique.
The experimental results revealed that a binding solution obtained
with the proposed method reduces 5.6-27.2% (18.0% on average) and
2.6-12.7% (6.8% on average) of the switching activity when compared
with conventional binding-only and hybrid binding-encoding
methods, respectively.
Abstract: A conventional binding method for low power in a
high-level synthesis mainly focuses on finding an optimal binding for
an assumed input data, and obtains only one binding table. In this
paper, we show that a binding method which uses multiple binding
tables gets better solution compared with the conventional methods
which use a single binding table, and propose a dynamic bus binding
scheme for low power using multiple binding tables. The proposed
method finds multiple binding tables for the proper partitions of an
input data, and switches binding tables dynamically to produce the
minimum total switching activity. Experimental result shows that the
proposed method obtains a binding solution having 12.6-28.9%
smaller total switching activity compared with the conventional
methods.
Abstract: In this paper, the problem of reducing switching
activity in on-chip buses at the stage of high-level synthesis is
considered, and a high-level low power bus binding based on dynamic
bit reordering is proposed. Whereas conventional methods use a fixed
bit ordering between variables within a bus, the proposed method
switches a bit ordering dynamically to obtain a switching activity
reduction. As a result, the proposed method finds a binding solution
with a smaller value of total switching activity (TSA). Experimental
result shows that the proposed method obtains a binding solution
having 12.0-34.9% smaller TSA compared with the conventional
methods.