Abstract: Versatile dual-mode class-AB CMOS four-quadrant
analog multiplier circuit is presented. The dual translinear loops and
current mirrors are the basic building blocks in realization scheme.
This technique provides; wide dynamic range, wide-bandwidth response
and low power consumption. The major advantages of this
approach are; its has single ended inputs; since its input is dual translinear
loop operate in class-AB mode which make this multiplier
configuration interesting for low-power applications; current multiplying,
voltage multiplying, or current and voltage multiplying can
be obtainable with balanced input. The simulation results of versatile
analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth
of about 19MHz, a maximum power consumption of 0.46mW,
and temperature compensated. Operation of versatile analog multiplier
was also confirmed through an experiment using CMOS transistor
array.
Abstract: We demonstrate a 1×4 coarse wavelength
division-multiplexing (CWDM) planar concave grating
multiplexer/demultiplexer and its application in re-configurable
optical add/drop multiplexer (ROADM) system in silicon-on-insulator
substrate. The wavelengths of the demonstrated concave grating
multiplexer align well with the ITU-T standard. We demonstrate a
prototype of ROADM comprising two such concave gratings and four
wide-band thermo-optical MZI switches. Undercut technology which
removes the underneath silicon substrate is adopted in optical switches
in order to minimize the operation power. For all the thermal heaters,
the operation voltage is smaller than 1.5 V, and the switch power is
~2.4 mW. High throughput pseudorandom binary sequence (PRBS)
data transmission with up to 100 Gb/s is demonstrated, showing the
high-performance ROADM functionality.
Abstract: The energy consumption of home femto base stations
(BSs) can be reduced, by turning off the Wi-Fi radio interface when
there is no mobile station (MS) under the coverage of the BSs or
MSs do not transmit or receive data packet for long time, especially
in late night. In the energy-efficient home femto BSs, if MSs have
any data packet to transmit and the Wi-Fi radio interface in off
state, MSs wake up the Wi-Fi radio interface of home femto BSs
by using additional low power radio interface. In this paper, the
performance of the energy-efficient home femto BSs from the aspect
of energy consumption and cumulative average delay, and show the
effect of various parameters on energy consumption and cumulative
average delay. From the results, the tradeoff relationship between
energy consumption and cumulative average delay is shown and thus,
appropriate operation should be needed to balance the tradeoff.
Abstract: A high-frequency low-power sinusoidal quadrature
oscillator is presented through the use of two 2nd-order low-pass
current-mirror (CM)-based filters, a 1st-order CM low-pass filter and
a CM bilinear transfer function. The technique is relatively simple
based on (i) inherent time constants of current mirrors, i.e. the
internal capacitances and the transconductance of a diode-connected
NMOS, (ii) a simple negative resistance RN formed by a resistor load
RL of a current mirror. Neither external capacitances nor inductances
are required. As a particular example, a 1.9-GHz, 0.45-mW, 2-V
CMOS low-pass-filter-based all-current-mirror sinusoidal quadrature
oscillator is demonstrated. The oscillation frequency (f0) is 1.9 GHz
and is current-tunable over a range of 370 MHz or 21.6 %. The
power consumption is at approximately 0.45 mW. The amplitude
matching and the quadrature phase matching are better than 0.05 dB
and 0.15°, respectively. Total harmonic distortions (THD) are less
than 0.3 %. At 2 MHz offset from the 1.9 GHz, the carrier to noise
ratio (CNR) is 90.01 dBc/Hz whilst the figure of merit called a
normalized carrier-to-noise ratio (CNRnorm) is 153.03 dBc/Hz. The
ratio of the oscillation frequency (f0) to the unity-gain frequency (fT)
of a transistor is 0.25. Comparisons to other approaches are also
included.