A Novel Low Power Digitally Controlled Oscillator with Improved linear Operating Range
In this paper, an ultra low power and low jitter 12bit
CMOS digitally controlled oscillator (DCO) design is presented.
Based on a ring oscillator implemented with low power Schmitt
trigger based inverters. Simulation of the proposed DCO using 32nm
CMOS Predictive Transistor Model (PTM) achieves controllable
frequency range of 550MHz~830MHz with a wide linearity and high
resolution. Monte Carlo simulation demonstrates that the time-period
jitter due to random power supply fluctuation is under 31ps and the
power consumption is 0.5677mW at 750MHz with 1.2V power
supply and 0.53-ps resolution. The proposed DCO has a good
robustness to voltage and temperature variations and better linearity
comparing to the conventional design.
[1] P.-L. Chen, C.-C. Chung, and C.-Y. Lee, "A portable digitally
controlled oscillator using novel varactors," IEEE Transactions on
Circuits and Systems II, vol. 52, no. 5, pp. 233-237, 2005.
[2] Roland E. Best: "Phase-locked loops. Theory, Design, and
applications," McGraw-Hill Book Company, 1984.
[3] B. Razavi, "Monolithic Phase-Locked Loops and Clock-Recovery
Circuits," IEEE Press, 1996. Collection of IEEE PLL papers.
[4] C. Chung and C. Lee, "An all-digital phase-locked loop for high-speed
clock generation," IEEE J. Solid-State Circuits, vol. 38, pp. 347-351,
Feb. 2003.
[5] P. Nilsson and M. Torkelson, "A monolithic digital clock-generator
for on-chip clocking of custom DSP-s," IEEE J. Solid-State Circuits,
vol.31, pp. 700-706, May 1996.
[6] J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, "An all-digital
phase-locked loop with 50-cycle lock time suitable for high
performance microprocessors," IEEE J. Solid-State Circuits, vol. 30, pp.
412-422, Apr. 1995.
[7] T.Olsson and P.nilsson, "A digitally controlled PLL for SoC
application," IEEE j. Solid-state Circuits, Vol.39, no. 5,pp.751-760,
May 2004.
[8] R. B. Staszewski and P. T. Balsar, " Phase-Domain All-Digital Phase-
Locked Loop,"IEEE Trans. Circuits and Systems II, Vol. 52, pp. 159-
163, Mar. 2005.
[9] M. Saint-Laurent et al, "A Digitally Controlled Oscillator Constructed
Using Adjustable Resistor," IEEE Southwest Symposium on Mixed-
Signal Design, 2001.
[10] P. Raha, S. Randall, R. Jennings, B. Helmick, A. Amerasekera, and
B.Haroun, "A robust digital delay line architecture in a 0.13-_m CMOS
technology node for reduced design and process sensitivities," in Proc.
ISQED-02, pp. 148-153, Mar. 2002.
[11] P. Andreani, F. Bigongiari, R Roncella, R. Saletti and P.Tenini, "A
Digitally Controlled Shunt Capacitor CMOS Delay Line," Analog
Circuits and Signal Processing, Kluwer Academic Publishers, Volume
18, pp. 89-96. 1999.
[12] T. Olsson and P. Nilsson, "Portable digital clock generator for digital
signal processing applications," Electron. Lett., vol. 39, pp. 1372-1374,
Sep. 2003.
[13] E. Roth, M. Thalmann, N. Felber, and W. Fichtner, "A delay-line based
DCO for multimedia applications using digital standard cells only," in
Dig. Tech. Papers ISSCC-03, Feb. 2003, pp. 432-433.
[14] V.A. Pedroni," Low-voltage high-speed Schmitt trigger and compact
window comparator," Electronics Letters, vol. 41 no. 22, Oct 2005.
[1] P.-L. Chen, C.-C. Chung, and C.-Y. Lee, "A portable digitally
controlled oscillator using novel varactors," IEEE Transactions on
Circuits and Systems II, vol. 52, no. 5, pp. 233-237, 2005.
[2] Roland E. Best: "Phase-locked loops. Theory, Design, and
applications," McGraw-Hill Book Company, 1984.
[3] B. Razavi, "Monolithic Phase-Locked Loops and Clock-Recovery
Circuits," IEEE Press, 1996. Collection of IEEE PLL papers.
[4] C. Chung and C. Lee, "An all-digital phase-locked loop for high-speed
clock generation," IEEE J. Solid-State Circuits, vol. 38, pp. 347-351,
Feb. 2003.
[5] P. Nilsson and M. Torkelson, "A monolithic digital clock-generator
for on-chip clocking of custom DSP-s," IEEE J. Solid-State Circuits,
vol.31, pp. 700-706, May 1996.
[6] J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, "An all-digital
phase-locked loop with 50-cycle lock time suitable for high
performance microprocessors," IEEE J. Solid-State Circuits, vol. 30, pp.
412-422, Apr. 1995.
[7] T.Olsson and P.nilsson, "A digitally controlled PLL for SoC
application," IEEE j. Solid-state Circuits, Vol.39, no. 5,pp.751-760,
May 2004.
[8] R. B. Staszewski and P. T. Balsar, " Phase-Domain All-Digital Phase-
Locked Loop,"IEEE Trans. Circuits and Systems II, Vol. 52, pp. 159-
163, Mar. 2005.
[9] M. Saint-Laurent et al, "A Digitally Controlled Oscillator Constructed
Using Adjustable Resistor," IEEE Southwest Symposium on Mixed-
Signal Design, 2001.
[10] P. Raha, S. Randall, R. Jennings, B. Helmick, A. Amerasekera, and
B.Haroun, "A robust digital delay line architecture in a 0.13-_m CMOS
technology node for reduced design and process sensitivities," in Proc.
ISQED-02, pp. 148-153, Mar. 2002.
[11] P. Andreani, F. Bigongiari, R Roncella, R. Saletti and P.Tenini, "A
Digitally Controlled Shunt Capacitor CMOS Delay Line," Analog
Circuits and Signal Processing, Kluwer Academic Publishers, Volume
18, pp. 89-96. 1999.
[12] T. Olsson and P. Nilsson, "Portable digital clock generator for digital
signal processing applications," Electron. Lett., vol. 39, pp. 1372-1374,
Sep. 2003.
[13] E. Roth, M. Thalmann, N. Felber, and W. Fichtner, "A delay-line based
DCO for multimedia applications using digital standard cells only," in
Dig. Tech. Papers ISSCC-03, Feb. 2003, pp. 432-433.
[14] V.A. Pedroni," Low-voltage high-speed Schmitt trigger and compact
window comparator," Electronics Letters, vol. 41 no. 22, Oct 2005.
@article{"International Journal of Electrical, Electronic and Communication Sciences:55323", author = "Nasser Erfani Majd and Mojtaba Lotfizad", title = "A Novel Low Power Digitally Controlled Oscillator with Improved linear Operating Range", abstract = "In this paper, an ultra low power and low jitter 12bit
CMOS digitally controlled oscillator (DCO) design is presented.
Based on a ring oscillator implemented with low power Schmitt
trigger based inverters. Simulation of the proposed DCO using 32nm
CMOS Predictive Transistor Model (PTM) achieves controllable
frequency range of 550MHz~830MHz with a wide linearity and high
resolution. Monte Carlo simulation demonstrates that the time-period
jitter due to random power supply fluctuation is under 31ps and the
power consumption is 0.5677mW at 750MHz with 1.2V power
supply and 0.53-ps resolution. The proposed DCO has a good
robustness to voltage and temperature variations and better linearity
comparing to the conventional design.", keywords = "digitally controlled oscillator (DCO), low power,jitter; good linearity, robust", volume = "5", number = "3", pages = "324-6", }