Abstract: Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.
Abstract: Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.
Abstract: According to IR, 13C and 1H NMR, APT, 1D NOE,
2D heteronuclear 1H/13C HSQC and 2D DOSY experiments the main
chemical constituent of high-molecular preparations from Symphytum
asperum, S. caucasicum, S. officinale and Anchusa italica
(Boraginaceae) was found to be caffeic acid-derived polyether,
namely poly[3-(3,4-dihydroxyphenyl)glyceric acid] (PDPGA) or
poly[oxy-1-carboxy-2-(3,4-dihydroxyphenyl)ethylene]. Most
carboxylic groups of this polymer of A. italica are methylated.
Abstract: The high-molecular water-soluble preparations from
several species of two genera (Symphytum and Anchusa) of
Boraginaceae family Symphytum asperum, S. caucasicum, S.officinale
and Anchusa italica were isolated. According to IR, 13C and 1H
NMR, APT, 1D NOE, 2D heteronuclear 1H/13C HSQC and 2D
DOSY experiments, the main chemical constituent of these
preparations was found to be caffeic acid-derived polyether, namely
poly[3-(3,4-dihydroxyphenyl)glyceric acid] (PDPGA) or poly[oxy-1-
carboxy-2-(3,4-dihydroxyphenyl)ethylene]. Most carboxylic groups
of this caffeic acid-derived polymer of A. italica are methylated.
Abstract: This research paper presents highly optimized barrel
shifter at 22nm Hi K metal gate strained Si technology node. This
barrel shifter is having a unique combination of static and dynamic
body bias which gives lowest power delay product. This power delay
product is compared with the same circuit at same technology node
with static forward biasing at ‘supply/2’ and also with normal reverse
substrate biasing and still found to be the lowest. The power delay
product of this barrel sifter is .39362X10-17J and is lowered by
approximately 78% to reference proposed barrel shifter at 32nm bulk
CMOS technology. Power delay product of barrel shifter at 22nm Hi
K Metal gate technology with normal reverse substrate bias is
2.97186933X10-17J and can be compared with this design’s PDP of
.39362X10-17J. This design uses both static and dynamic substrate
biasing and also has approximately 96% lower power delay product
compared to only forward body biased at half of supply voltage. The
NMOS model used are predictive technology models of Arizona state
university and the simulations to be carried out using HSPICE
simulator.
Abstract: The Smart Help for persons with disability (PWD) is a
part of the project SMARTDISABLE which aims to develop relevant
solution for PWD that target to provide an adequate workplace
environment for them. It would support PWD needs smartly through
smart help to allow them access to relevant information and
communicate with other effectively and flexibly, and smart editor
that assist them in their daily work. It will assist PWD in knowledge
processing and creation as well as being able to be productive at the
work place. The technical work of the project involves design of a
technological scenario for the Ambient Intelligence (AmI) - based
assistive technologies at the workplace consisting of an integrated
universal smart solution that suits many different impairment
conditions and will be designed to empower the Physically disabled
persons (PDP) with the capability to access and effectively utilize the
ICTs in order to execute knowledge rich working tasks with
minimum efforts and with sufficient comfort level. The proposed
technology solution for PWD will support voice recognition along
with normal keyboard and mouse to control the smart help and smart
editor with dynamic auto display interface that satisfies the
requirements for different PWD group. In addition, a smart help will
provide intelligent intervention based on the behavior of PWD to
guide them and warn them about possible misbehavior. PWD can
communicate with others using Voice over IP controlled by voice
recognition. Moreover, Auto Emergency Help Response would be
supported to assist PWD in case of emergency. This proposed
technology solution intended to make PWD very effective at the
work environment and flexible using voice to conduct their tasks at
the work environment. The proposed solution aims to provide
favorable outcomes that assist PWD at the work place, with the
opportunity to participate in PWD assistive technology innovation
market which is still small and rapidly growing as well as upgrading
their quality of life to become similar to the normal people at the
workplace. Finally, the proposed smart help solution is applicable in
all workplace setting, including offices, manufacturing, hospital, etc.
Abstract: In this paper, a design methodology to implement low-power and high-speed 2nd order recursive digital Infinite Impulse Response (IIR) filter has been proposed. Since IIR filters suffer from a large number of constant multiplications, the proposed method replaces the constant multiplications by using addition/subtraction and shift operations. The proposed new 6T adder cell is used as the Carry-Save Adder (CSA) to implement addition/subtraction operations in the design of recursive section IIR filter to reduce the propagation delay. Furthermore, high-level algorithms designed for the optimization of the number of CSA blocks are used to reduce the complexity of the IIR filter. The DSCH3 tool is used to generate the schematic of the proposed 6T CSA based shift-adds architecture design and it is analyzed by using Microwind CAD tool to synthesize low-complexity and high-speed IIR filters. The proposed design outperforms in terms of power, propagation delay, area and throughput when compared with MUX-12T, MCIT-7T based CSA adder filter design. It is observed from the experimental results that the proposed 6T based design method can find better IIR filter designs in terms of power and delay than those obtained by using efficient general multipliers.
Abstract: Citizens are increasingly are provided with choice and
customization in public services and this has now also become a key
feature of higher education in terms of policy roll-outs on personal
development planning (PDP) and more generally as part of the
employability agenda. The goal here is to transform people, in this
case graduates, into active, responsible citizen-workers. A key part of
this rhetoric and logic is the inculcation of graduate attributes within
students. However, there has also been a concern with the issue of
student lack of engagement and perseverance with their studies. This
paper sets out to explore some of these conceptions that link graduate
attributes with citizenship as well as the notion of how identity is
forged through the higher education process. Examples are drawn
from a quality enhancement project that is being operated within the
context of the Scottish higher education system. This is further
framed within the wider context of competing and conflicting
demands on higher education, exacerbated by the current worldwide
economic climate. There are now pressures on students to develop
their employability skills as well as their capacity to engage with
global issues such as behavioural change in the light of
environmental concerns. It is argued that these pressures, in effect,
lead to a form of personalization that is concerned with how
graduates develop their sense of identity as something that is
engineered and re-engineered to meet these demands.
Abstract: As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.
Abstract: New methodologies for XOR-XNOR circuits are
proposed to improve the speed and power as these circuits are basic
building blocks of many arithmetic circuits. This paper evaluates and
compares the performance of various XOR-XNOR circuits. The
performance of the XOR-XNOR circuits based on TSMC 0.18μm
process models at all range of the supply voltage starting from 0.6V
to 3.3V is evaluated by the comparison of the simulation results
obtained from HSPICE. Simulation results reveal that the proposed
circuit exhibit lower PDP and EDP, more power efficient and faster
when compared with best available XOR-XNOR circuits in the
literature.
Abstract: In diversity rich environments, such as in Ultra-
Wideband (UWB) applications, the a priori determination of the
number of strong diversity branches is difficult, because of the considerably large number of diversity paths, which are characterized
by a variety of power delay profiles (PDPs). Several
Rake implementations have been proposed in the past, in order to reduce the number of the estimated and combined paths. To this
aim, we introduce two adaptive Rake receivers, which combine
a subset of the resolvable paths considering simultaneously the
quality of both the total combining output signal-to-noise ratio (SNR) and the individual SNR of each path. These schemes achieve
better adaptation to channel conditions compared to other known receivers, without further increasing the complexity. Their performance
is evaluated in different practical UWB channels, whose models are based on extensive propagation measurements. The
proposed receivers compromise between the power consumption,
complexity and performance gain for the additional paths, resulting in important savings in power and computational resources.
Abstract: The proposed multiplexer-based novel 1-bit full
adder cell is schematized by using DSCH2 and its layout is generated
by using microwind VLSI CAD tool. The adder cell layout
interconnect analysis is performed by using BSIM4 layout analyzer.
The adder circuit is compared with other six existing adder circuits
for parametric analysis. The proposed adder cell gives better
performance than the other existing six adder circuits in terms of
power, propagation delay and PDP. The proposed adder circuit is
further analyzed for interconnect analysis, which gives better
performance than other adder circuits in terms of layout thickness,
width and height.
Abstract: In this paper we present two novel 1-bit full adder
cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output
structures are used to design the adder blocks. Characteristic of
dynamic logic leads to higher speeds than the other standard static
full adder cells. Using HSpice and 0.18┬Ám CMOS technology
exhibits a significant decrease in the cell delay which can result in a
considerable reduction in the power-delay product (PDP). The PDP
of Multi-Output design at 1.8v power supply is around 0.15 femto
joule that is 5% lower than conventional dynamic full adder cell and
at least 21% lower than other static full adders.
Abstract: Custom power is a technology driven product and
service solution which embraces a family devices such as Dynamic
Voltage Restorer (DVR), Distributed Shunt Compensator
(DSTATCOM), Solid State Breaker (SSB) etc which will provide
power quality functions at distribution voltages. The rapid response
of these devices enables them to operate in real time, providing
continuous and dynamic control of the supply including voltage and
reactive power regulation, harmonic reduction and elimination of
voltage dips. This paper presents the benefits of multilevel inverters
when they are used for DPC based custom power devices. Power
flow control mechanism, salient features, advantages and
disadvantages of direct power control (DPC) using lookup table,
SVM, predictive voltage vector and hybrid DPC strategies are
discussed in this paper. Simulation results of three level inverter
based STATCOM, harmonic analysis of multi level inverters are
presented at the end.
Abstract: The product development process (PDP) in the
Technology group plays a very important role in the launch of any
product. While a manufacturing process encourages the use of certain
measures to reduce health, safety and environmental (HSE) risks on
the shop floor, the PDP concentrates on the use of Geometric
Dimensioning and Tolerancing (GD&T) to develop a flawless design.
Furthermore, PDP distributes and coordinates activities between
different departments such as marketing, purchasing, and
manufacturing. However, it is seldom realized that PDP makes a
significant contribution to developing a product that reduces HSE
risks by encouraging the Technology group to use effective GD&T.
The GD&T is a precise communication tool that uses a set of
symbols, rules, and definitions to mathematically define parts to be
manufactured. It is a quality assurance method widely used in the oil
and gas sector. Traditionally it is used to ensure the
interchangeability of a part without affecting its form, fit, and
function. Parts that do not meet these requirements are rejected
during quality audits.
This paper discusses how the Technology group integrates this
quality assurance tool into the PDP and how the tool plays a major
role in helping the HSE department in its goal towards eliminating
HSE incidents. The PDP involves a thorough risk assessment and
establishes a method to address those risks during the design stage.
An illustration shows how GD&T helped reduce safety risks by
ergonomically improving assembling operations. A brief discussion
explains how tolerances provided on a part help prevent finger injury.
This tool has equipped Technology to produce fixtures, which are
used daily in operations as well as manufacturing. By applying
GD&T to create good fits, HSE risks are mitigated for operating
personnel. Both customers and service providers benefit from
reduced safety risks.