Optimizing the Performance of Thermoelectric for Cooling Computer Chips Using Different Types of Electrical Pulses
Thermoelectric technology is currently being used in many industrial applications for cooling, heating and generating electricity. This research mainly focuses on using thermoelectric to cool down high-speed computer chips at different operating conditions. A previously developed and validated three-dimensional model for optimizing and assessing the performance of cascaded thermoelectric and non-cascaded thermoelectric is used in this study to investigate the possibility of decreasing the hotspot temperature of computer chip. Additionally, a test assembly is built and tested at steady-state and transient conditions. The obtained optimum thermoelectric current at steady-state condition is used to conduct a number of pulsed tests (i.e. transient tests) with different shapes to cool the computer chips hotspots. The results of the steady-state tests showed that at hotspot heat rate of 15.58 W (5.97 W/cm2), using thermoelectric current of 4.5 A has resulted in decreasing the hotspot temperature at open circuit condition (89.3 °C) by 50.1 °C. Maximum and minimum hotspot temperatures have been affected by ON and OFF duration of the electrical current pulse. Maximum hotspot temperature was resulted by longer OFF pulse period. In addition, longer ON pulse period has generated the minimum hotspot temperature.
[1] ITRS, International Technology Roadmap for Semiconductors, 2004.
[2] R. Viswanath, W. Vijay, A. Watweand V. Lebonheur, “Thermal performance challenges from silicon to systems,” Intel Technol. J., 4 (3), pp. 1–16, 2000.
[3] B. Goplen and S. S. Sapatnekar, “Placement of thermal vias in 3D ICs using various thermal objectives,” IEEE Trans. Comput. Aided Design Integ. Circuits Syst., 26 (4), pp. 692–709, 2006.
[4] H. F. Hamann, A. Weger, J. A. Lacey, Z. Hu, P. Bose, E. Cohen and J. Wakil, “Hotspot limited microprocessors: Direct temperature and power distribution measurements,” IEEE J. Solid-State Circuits, 42 (1), pp. 56–65, 2007.
[5] I. Chowdhury, R. Prasher, K. Lofgreen, G. Chrysler, S. Narasimhan, R. Mahajan, D. Koester, R. Alley and R. Venkatasubramanian, “On-chip cooling by superlattice-based thin-film thermoelectrics,” Nature Nanotechnol., 4 (4), pp. 235–238, 2009.
[6] S. V. Garimella, V. Singhal and D. Liu, “On-chip thermal management with microchannel heat sinks and integrated micropumps,” Proc. IEEE, 94 (8), pp. 1534–1548, 2006.
[7] C. Green, A. G. Fedorov and Y. K. Joshi, “Fluid-to-fluid spot-to-spreader (F2/S2) hybrid heat sink for integrated chip-level and hotspot level thermal management,” ASME J. Ele. Packag., 131 (2), pp. 025002-1–025002-10, 2009.
[8] V. Sahu, Y. Joshi and A. Fedorov, “Hybrid solid state/fluidic cooling for hot spot removal,” Nanoscale Microscale Thermophys. Eng., 13 (3), pp. 135–150, 2009.
[9] N. Putra, Yanuar and F. N. Iskandar, “Application of nanofluids to a heat pipe liquid-block and the thermoelectric cooling of electronic equipment,” Experimental Thermal and Fluid Science, vol. 35, pp. 1274–1281, 2011.
[10] P. Wang, A. Bar-Cohen, B. Yang, G. L. Solbrekken and A. Shakouri, “Analytical Modeling of Silicon Thermoelectric Microcooler,” J. Appl. Phys., 100, p. 014501, 2006.
[11] V. Litivinovitch and A. B. Cohen, “Effect of Thermal Contact Resistance on Optimum Mini-contact TEC Cooling on On-chip Hot Spots,” Proceedings of InterPACK0’9, San Francisco, CA, 2009.
[12] Y. S. Ju, “Impact of Interface Resistance on Pulsed Thermoelectric cooling,” J. Heat Trans., 130, p. 014502, 2008.
[13] O. Sullivan, M. P. Gupta,S. Mukhhyopadhyay and S. Kumar, "Array of Thermoelectric Coolers for On-Chip Thermal Management," Journal of Electronic Packaging, 134, pp. 1-8, 2012.
[14] R. Cheinand G. Huang, “Thermoelectric cooler application in electronic cooling,” Applied Thermal Engineering, vol. 24, p. 2207–2217, 2004.
[15] Thermoelectrics Handbook: Macro to Nano, Edited by D.M. Rowe, CRC Press, Taylor & Francis Group, ISBN 0-8493-2264-2, 2006.
[16] R. S. Prasher, J. –Y. Chang, I. Sauciuc, S. Narasimhan, D. Chau, G. Chrysler, A. Myers, S. Prstic and C. Hu, “Nano and micro technology based next-generation package-level cooling solutions,” Int. Technol. J., 9 (4), pp. 285–296, 2005.
[17] S. V. Garimella, “Advances in Mesoscale Thermal Management Technologies for Microelectronics,” Microelectron. J., 37, pp. 1165–1185, 2006.
[18] L. M. Goncalves, J. G. Rocha, D. Couto, P. Alpuimand J. H. Correia, “On-chip Array of Thermoelectric Peltier Microcoolers,” Sens. Actuators, A145-146, pp. 75–80, 2008.
[19] M. P. Gupta, M. S. Sayer, S. Mukhopadhyayand S. Kumar, “Ultrathin Thermoelectric Devices for On-chip Peltier Cooling,” IEEE Trans. Compon., Packag. Manuf. Technol., 1(9), pp. 1395–1405, 2011.
[20] A. Bar-Cohen and P. Wang, “On-chip hot spot remediation with miniaturized thermoelectric coolers,” Micrograv, Sci, Technol, 21 (1), pp. 351–359, 2009.
[21] M. Redmond, K. Manickaraj, O. Sullivan and S. Kumar, “Hotspot Cooling in Stacked Chips Using Thermoelectric Coolers," IEEE Transactions on Components, Packaging and Manufacturing Technology, 3 (5), pp. 759-767, 2013.
[22] G. J. Snyder,M. Soto,R. Alley,D. Koester and B. Conner, “Hot Spot Cooling using Embedded Thermoelectric Coolers,” in Twenty-Second Annual IEEE Semiconductor Thermal Measurement and Management Symposium, Dallas, TX USA, 2006.
[23] S. A. Alshehri and H. H. Saber, “Experimental investigation of using thermoelectric cooling for computer chips”, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009, 2019 (in press).
[24] S. A. Alshehri, “Cooling Computer Chips with Cascaded and Non-Cascaded Thermoelectric Devices”, Arabian Journal for Science and Engineering, https://doi.org/10.1007/s13369-019-03862-2, 2019.
[25] H. H. Saber, S. A. Alshehri and W. Maref, “Performance optimization of cascaded and non-cascaded thermoelectric devices for cooling computer chips”, Journal of Energy Conversion and Management, https://www.sciencedirect.com/science/article/pii/S0196890419304406, 191, p. 174–192, 2019.
[1] ITRS, International Technology Roadmap for Semiconductors, 2004.
[2] R. Viswanath, W. Vijay, A. Watweand V. Lebonheur, “Thermal performance challenges from silicon to systems,” Intel Technol. J., 4 (3), pp. 1–16, 2000.
[3] B. Goplen and S. S. Sapatnekar, “Placement of thermal vias in 3D ICs using various thermal objectives,” IEEE Trans. Comput. Aided Design Integ. Circuits Syst., 26 (4), pp. 692–709, 2006.
[4] H. F. Hamann, A. Weger, J. A. Lacey, Z. Hu, P. Bose, E. Cohen and J. Wakil, “Hotspot limited microprocessors: Direct temperature and power distribution measurements,” IEEE J. Solid-State Circuits, 42 (1), pp. 56–65, 2007.
[5] I. Chowdhury, R. Prasher, K. Lofgreen, G. Chrysler, S. Narasimhan, R. Mahajan, D. Koester, R. Alley and R. Venkatasubramanian, “On-chip cooling by superlattice-based thin-film thermoelectrics,” Nature Nanotechnol., 4 (4), pp. 235–238, 2009.
[6] S. V. Garimella, V. Singhal and D. Liu, “On-chip thermal management with microchannel heat sinks and integrated micropumps,” Proc. IEEE, 94 (8), pp. 1534–1548, 2006.
[7] C. Green, A. G. Fedorov and Y. K. Joshi, “Fluid-to-fluid spot-to-spreader (F2/S2) hybrid heat sink for integrated chip-level and hotspot level thermal management,” ASME J. Ele. Packag., 131 (2), pp. 025002-1–025002-10, 2009.
[8] V. Sahu, Y. Joshi and A. Fedorov, “Hybrid solid state/fluidic cooling for hot spot removal,” Nanoscale Microscale Thermophys. Eng., 13 (3), pp. 135–150, 2009.
[9] N. Putra, Yanuar and F. N. Iskandar, “Application of nanofluids to a heat pipe liquid-block and the thermoelectric cooling of electronic equipment,” Experimental Thermal and Fluid Science, vol. 35, pp. 1274–1281, 2011.
[10] P. Wang, A. Bar-Cohen, B. Yang, G. L. Solbrekken and A. Shakouri, “Analytical Modeling of Silicon Thermoelectric Microcooler,” J. Appl. Phys., 100, p. 014501, 2006.
[11] V. Litivinovitch and A. B. Cohen, “Effect of Thermal Contact Resistance on Optimum Mini-contact TEC Cooling on On-chip Hot Spots,” Proceedings of InterPACK0’9, San Francisco, CA, 2009.
[12] Y. S. Ju, “Impact of Interface Resistance on Pulsed Thermoelectric cooling,” J. Heat Trans., 130, p. 014502, 2008.
[13] O. Sullivan, M. P. Gupta,S. Mukhhyopadhyay and S. Kumar, "Array of Thermoelectric Coolers for On-Chip Thermal Management," Journal of Electronic Packaging, 134, pp. 1-8, 2012.
[14] R. Cheinand G. Huang, “Thermoelectric cooler application in electronic cooling,” Applied Thermal Engineering, vol. 24, p. 2207–2217, 2004.
[15] Thermoelectrics Handbook: Macro to Nano, Edited by D.M. Rowe, CRC Press, Taylor & Francis Group, ISBN 0-8493-2264-2, 2006.
[16] R. S. Prasher, J. –Y. Chang, I. Sauciuc, S. Narasimhan, D. Chau, G. Chrysler, A. Myers, S. Prstic and C. Hu, “Nano and micro technology based next-generation package-level cooling solutions,” Int. Technol. J., 9 (4), pp. 285–296, 2005.
[17] S. V. Garimella, “Advances in Mesoscale Thermal Management Technologies for Microelectronics,” Microelectron. J., 37, pp. 1165–1185, 2006.
[18] L. M. Goncalves, J. G. Rocha, D. Couto, P. Alpuimand J. H. Correia, “On-chip Array of Thermoelectric Peltier Microcoolers,” Sens. Actuators, A145-146, pp. 75–80, 2008.
[19] M. P. Gupta, M. S. Sayer, S. Mukhopadhyayand S. Kumar, “Ultrathin Thermoelectric Devices for On-chip Peltier Cooling,” IEEE Trans. Compon., Packag. Manuf. Technol., 1(9), pp. 1395–1405, 2011.
[20] A. Bar-Cohen and P. Wang, “On-chip hot spot remediation with miniaturized thermoelectric coolers,” Micrograv, Sci, Technol, 21 (1), pp. 351–359, 2009.
[21] M. Redmond, K. Manickaraj, O. Sullivan and S. Kumar, “Hotspot Cooling in Stacked Chips Using Thermoelectric Coolers," IEEE Transactions on Components, Packaging and Manufacturing Technology, 3 (5), pp. 759-767, 2013.
[22] G. J. Snyder,M. Soto,R. Alley,D. Koester and B. Conner, “Hot Spot Cooling using Embedded Thermoelectric Coolers,” in Twenty-Second Annual IEEE Semiconductor Thermal Measurement and Management Symposium, Dallas, TX USA, 2006.
[23] S. A. Alshehri and H. H. Saber, “Experimental investigation of using thermoelectric cooling for computer chips”, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009, 2019 (in press).
[24] S. A. Alshehri, “Cooling Computer Chips with Cascaded and Non-Cascaded Thermoelectric Devices”, Arabian Journal for Science and Engineering, https://doi.org/10.1007/s13369-019-03862-2, 2019.
[25] H. H. Saber, S. A. Alshehri and W. Maref, “Performance optimization of cascaded and non-cascaded thermoelectric devices for cooling computer chips”, Journal of Energy Conversion and Management, https://www.sciencedirect.com/science/article/pii/S0196890419304406, 191, p. 174–192, 2019.
@article{"International Journal of Information, Control and Computer Sciences:79773", author = "Saleh Alshehri", title = "Optimizing the Performance of Thermoelectric for Cooling Computer Chips Using Different Types of Electrical Pulses", abstract = "Thermoelectric technology is currently being used in many industrial applications for cooling, heating and generating electricity. This research mainly focuses on using thermoelectric to cool down high-speed computer chips at different operating conditions. A previously developed and validated three-dimensional model for optimizing and assessing the performance of cascaded thermoelectric and non-cascaded thermoelectric is used in this study to investigate the possibility of decreasing the hotspot temperature of computer chip. Additionally, a test assembly is built and tested at steady-state and transient conditions. The obtained optimum thermoelectric current at steady-state condition is used to conduct a number of pulsed tests (i.e. transient tests) with different shapes to cool the computer chips hotspots. The results of the steady-state tests showed that at hotspot heat rate of 15.58 W (5.97 W/cm2), using thermoelectric current of 4.5 A has resulted in decreasing the hotspot temperature at open circuit condition (89.3 °C) by 50.1 °C. Maximum and minimum hotspot temperatures have been affected by ON and OFF duration of the electrical current pulse. Maximum hotspot temperature was resulted by longer OFF pulse period. In addition, longer ON pulse period has generated the minimum hotspot temperature.
", keywords = "Thermoelectric generator, thermoelectric cooler, chip hotspots, electronic cooling. ", volume = "14", number = "8", pages = "282-5", }
