Dual-Link Hierarchical Cluster-Based Interconnect Architecture for 3D Network on Chip

Network on Chip (NoC) has emerged as a promising on chip communication infrastructure. Three Dimensional Integrate Circuit (3D IC) provides small interconnection length between layers and the interconnect scalability in the third dimension, which can further improve the performance of NoC. Therefore, in this paper, a hierarchical cluster-based interconnect architecture is merged with the 3D IC. This interconnect architecture significantly reduces the number of long wires. Since this architecture only has approximately a quarter of routers in 3D mesh-based architecture, the average number of hops is smaller, which leads to lower latency and higher throughput. Moreover, smaller number of routers decreases the area overhead. Meanwhile, some dual links are inserted into the bottlenecks of communication to improve the performance of NoC. Simulation results demonstrate our theoretical analysis and show the advantages of our proposed architecture in latency, throughput and area, when compared with 3D mesh-based architecture.

Authors:

• Guang Sun
• Yong Li
• Yuanyuan Zhang
• Shijun Lin
• Li Su
• Depeng Jin
• Lieguang zeng

Keywords:

• Network on Chip (NoC)
• interconnect architecture
• performance
• area
• Three Dimensional Integrate Circuit (3D IC).

References:

[1] Hu. Jingcao and R. Marculescu, Energy-aware mapping for tile-based
NoC architectures under performance constraints, Proceedings of the
ASP-DAC 2003, pp.233-239, 2003.
[2] L. Benini and G. Micheli, Networks on chips: a new SoC paradigm,
IEEE Comput, vol.35, 2002.
[3] R. Marculescu, U.Y. Ogras, Peh. Li-Shiuan, N.E. Jerger, and Y.
Hoskote, Outstanding research problems in NoC design: system, microarchitecture,
and circuit perspectives, IEEE Transactions on Computer-
Aided Design of Integrated Circuits and Systems, vol.28, pp. 3-21, 2009.
[4] C. Marcon and A. Borin, Time and energy efficient mapping of embedded
applications onto NoCs, ASP-DAC 2005, pp.33-38, 2005.
[5] S. Murali, M. Coenen, A. Radulescu, K. Goossens and G. De Micheli,
A methodology for mapping multiple use-cases onto networks on chips,
Proc. Des. Autom. Test Eur. Conf 2006, pp.118-123, 2006.
[6] H. G. Lee, N. Chang, U. Y. Ogras and R. Marculescu, On-chip
communication architecture exploration: a quantitative evaluation of
point-to-point, bus, and network-on-chip approaches, ACM Trans. Des.
Autom.Electron. Syst, vol.12, pp.20-40, 2007.
[7] M. Horowitz, R. Ho, and K. Mai, The future of wires, Proc.
IEEE,vol.89, pp.490-504, 2001.
[8] J. Kim, W.J. Dally and D. Abts, Flattened butterfly: a cost-efficient
topology for high-radix networks, Proceedings of the 34th annual
international symposium on Computer architecture, pp.126-137,2007.
[9] V.F. Pavlidis and E.G. Friedman, 3-D topologies for networks-on-chip,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol.15, no.10, pp.1081-1090, 2007.
[10] Z. Yu, and B.M. Baas, A Low-Area Multi-Link Interconnect Architecture
for GALS Chip Multiprocessors, IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol.18, no.5, pp.750-762, 2010.
[11] WJ. Dally and B. Towles, Route packets, not wires: On-chip interconnection
networks, Design Automation Conference, 2001. Proceedings,
pp.684-689, 2001.
[12] P.P. Pande, C. Grecu, M. Jones, A. Ivanov and R. Saleh, Performance
evaluation and design trade-offs for network-on-chip interconnect architectures,
IEEE Transactions on Computers, vol.54, no.8, pp.1025-1040,
2005.