Abstract: This paper presents a novel CMOS four-transistor
SRAM cell for very high density and low power embedded SRAM
applications as well as for stand-alone SRAM applications. This cell
retains its data with leakage current and positive feedback without
refresh cycle. The new cell size is 20% smaller than a conventional
six-transistor cell using same design rules. Also proposed cell uses
two word-lines and one pair bit-line. Read operation perform from
one side of cell, and write operation perform from another side of
cell, and swing voltage reduced on word-lines thus dynamic power
during read/write operation reduced. The fabrication process is fully
compatible with high-performance CMOS logic technologies,
because there is no need to integrate a poly-Si resistor or a TFT load.
HSPICE simulation in standard 0.25μm CMOS technology confirms
all results obtained from this paper.
Abstract: With rapid technology scaling, the proportion of the
static power consumption catches up with dynamic power
consumption gradually. To decrease leakage consumption is
becoming more and more important in low-power design. This paper
presents a power-gating scheme for P-DTGAL (p-type dual
transmission gate adiabatic logic) circuits to reduce leakage power
dissipations under deep submicron process. The energy dissipations of
P-DTGAL circuits with power-gating scheme are investigated in
different processes, frequencies and active ratios. BSIM4 model is
adopted to reflect the characteristics of the leakage currents. HSPICE
simulations show that the leakage loss is greatly reduced by using the
P-DTGAL with power-gating techniques.
Abstract: The flash memory has many advantages such as low power consumption, strong shock resistance, fast I/O and non-volatility. And it is increasingly used in the mobile storage device. The YAFFS, one of the NAND flash file system, is widely used in the embedded device. However, the existing YAFFS takes long time to mount the file system because it scans whole spare areas in all pages of NAND flash memory. In order to solve this problem, we propose a new content-based flash file system using a mounting time reduction technique. The proposed method only scans partial spare areas of some special pages by using content-based block management. The experimental results show that the proposed method reduces the average mounting time by 87.2% comparing with JFFS2 and 69.9% comparing with YAFFS.
Abstract: Every day human life experiences new equipments
more automatic and with more abilities. So the need for faster
processors doesn-t seem to finish. Despite new architectures and
higher frequencies, a single processor is not adequate for many
applications. Parallel processing and networks are previous solutions
for this problem. The new solution to put a network of resources on a
chip is called NOC (network on a chip). The more usual topology for
NOC is mesh topology. There are several routing algorithms suitable
for this topology such as XY, fully adaptive, etc. In this paper we
have suggested a new algorithm named Intermittent X, Y (IX/Y). We
have developed the new algorithm in simulation environment to
compare delay and power consumption with elders' algorithms.
Abstract: In ad hoc networks, the main issue about designing of protocols is quality of service, so that in wireless sensor networks the main constraint in designing protocols is limited energy of sensors. In fact, protocols which minimize the power consumption in sensors are more considered in wireless sensor networks. One approach of reducing energy consumption in wireless sensor networks is to reduce the number of packages that are transmitted in network. The technique of collecting data that combines related data and prevent transmission of additional packages in network can be effective in the reducing of transmitted packages- number. According to this fact that information processing consumes less power than information transmitting, Data Aggregation has great importance and because of this fact this technique is used in many protocols [5]. One of the Data Aggregation techniques is to use Data Aggregation tree. But finding one optimum Data Aggregation tree to collect data in networks with one sink is a NP-hard problem. In the Data Aggregation technique, related information packages are combined in intermediate nodes and form one package. So the number of packages which are transmitted in network reduces and therefore, less energy will be consumed that at last results in improvement of longevity of network. Heuristic methods are used in order to solve the NP-hard problem that one of these optimization methods is to solve Simulated Annealing problems. In this article, we will propose new method in order to build data collection tree in wireless sensor networks by using Simulated Annealing algorithm and we will evaluate its efficiency whit Genetic Algorithm.
Abstract: with increasing circuits- complexity and demand to
use portable devices, power consumption is one of the most
important parameters these days. Full adders are the basic block of
many circuits. Therefore reducing power consumption in full adders
is very important in low power circuits. One of the most powerconsuming
modules in full adders is XOR/XNOR circuit. This paper
presents two new full adders based on two new logic approaches. The
proposed logic approaches use one XOR or XNOR gate to implement
a full adder cell. Therefore, delay and power will be decreased. Using
two new approaches and two XOR and XNOR gates, two new full
adders have been implemented in this paper. Simulations are carried
out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage.
The results show that the ten-transistors proposed full adder has 12%
less power consumption and is 5% faster in comparison to MB12T
full adder. 9T is more efficient in area and is 24% better than similar
10T full adder in term of power consumption. The main drawback of
the proposed circuits is output threshold loss problem.
Abstract: An approach and its implementation in 0.18 m CMOS process of the multichannel ASIC for capacitive (up to 30 pF) sensors are described in the paper. The main design aim was to study an analog data-driven architecture. The design was done for an analog derandomizing function of the 128 to 16 structure. That means that the ASIC structure should provide a parallel front-end readout of 128 input analog sensor signals and after the corresponding fast commutation with appropriate arbitration logic their processing by means of 16 output chains, including analog-to-digital conversion. The principal feature of the ASIC is a low power consumption within 2 mW/channel (including a 9-bit 20Ms/s ADC) at a maximum average channel hit rate not less than 150 kHz.
Abstract: In this paper, a alternative structure method for
continuous time sigma delta modulator is presented. In this
modulator for implementation of integrators in loop filter second
generation current conveyors are employed. The modulator is
designed in CMOS technology and features low power consumption
(65db),
and with 180khZ bandwidth. Simulation results confirm that this
design is suitable for data converters.
Abstract: In Image processing the Image compression can improve
the performance of the digital systems by reducing the cost and
time in image storage and transmission without significant reduction
of the Image quality. This paper describes hardware architecture of
low complexity Discrete Cosine Transform (DCT) architecture for
image compression[6]. In this DCT architecture, common computations
are identified and shared to remove redundant computations
in DCT matrix operation. Vector processing is a method used for
implementation of DCT. This reduction in computational complexity
of 2D DCT reduces power consumption. The 2D DCT is performed
on 8x8 matrix using two 1-Dimensional Discrete cosine transform
blocks and a transposition memory [7]. Inverse discrete cosine
transform (IDCT) is performed to obtain the image matrix and
reconstruct the original image. The proposed image compression
algorithm is comprehended using MATLAB code. The VLSI design
of the architecture is implemented Using Verilog HDL. The proposed
hardware architecture for image compression employing DCT was
synthesized using RTL complier and it was mapped using 180nm
standard cells. . The Simulation is done using Modelsim. The
simulation results from MATLAB and Verilog HDL are compared.
Detailed analysis for power and area was done using RTL compiler
from CADENCE. Power consumption of DCT core is reduced to
1.027mW with minimum area[1].
Abstract: Current mode circuits like current conveyors are
getting significant attention in current analog ICs design due to their
higher band-width, greater linearity, larger dynamic range, simpler
circuitry, lower power consumption and less chip area. The second
generation current controlled conveyor (CCCII) has the advantage of
electronic adjustability over the CCII i.e. in CCCII; adjustment of the
X-terminal intrinsic resistance via a bias current is possible. The
presented approach is based on the CMOS implementation of second
generation positive (CCCII+), negative (CCCII-) and dual Output
Current Controlled Conveyor (DOCCCII) and its application as
Universal filter. All the circuits have been designed and simulated
using 65nm CMOS technology model parameters on Cadence
Virtuoso / Spectre using 1V supply voltage. Various simulations have
been carried out to verify the linearity between output and input
ports, range of operation frequency, etc. The outcomes show good
agreement between expected and experimental results.
Abstract: A linear feedback shift register (LFSR) is proposed which targets to reduce the power consumption from within. It reduces the power consumption during testing of a Circuit Under Test (CUT) at two stages. At first stage,
Control Logic (CL) makes the clocks of the switching units
of the register inactive for a time period when output from
them is going to be same as previous one and thus reducing
unnecessary switching of the flip-flops. And at second stage,
the LFSR reorders the test vectors by interchanging the bit
with its next and closest neighbor bit. It keeps fault coverage
capacity of the vectors unchanged but reduces the Total Hamming Distance (THD) so that there is reduction in power
while shifting operation.
Abstract: In this paper, for the first time, a two-dimensional
(2D) analytical drain current model for sub-100 nm multi-layered
gate material engineered trapezoidal recessed channel (MLGMETRC)
MOSFET: a novel design is presented and investigated using
ATLAS and DEVEDIT device simulators, to mitigate the large gate
leakages and increased standby power consumption that arise due to
continued scaling of SiO2-based gate dielectrics. The twodimensional
(2D) analytical model based on solution of Poisson-s
equation in cylindrical coordinates, utilizing the cylindrical
approximation, has been developed which evaluate the surface
potential, electric field, drain current, switching metric: ION/IOFF
ratio and transconductance for the proposed design. A good
agreement between the model predictions and device simulation
results is obtained, verifying the accuracy of the proposed analytical
model.
Abstract: In this paper, an ultra low power and low jitter 12bit
CMOS digitally controlled oscillator (DCO) design is presented.
Based on a ring oscillator implemented with low power Schmitt
trigger based inverters. Simulation of the proposed DCO using 32nm
CMOS Predictive Transistor Model (PTM) achieves controllable
frequency range of 550MHz~830MHz with a wide linearity and high
resolution. Monte Carlo simulation demonstrates that the time-period
jitter due to random power supply fluctuation is under 31ps and the
power consumption is 0.5677mW at 750MHz with 1.2V power
supply and 0.53-ps resolution. The proposed DCO has a good
robustness to voltage and temperature variations and better linearity
comparing to the conventional design.
Abstract: This paper deals with a power-conscious ANDEXOR- Inverter type logic implementation for a complex class of Boolean functions, namely Achilles- heel functions. Different variants of the above function class have been considered viz. positive, negative and pure horn for analysis and simulation purposes. The proposed realization is compared with the decomposed implementation corresponding to an existing standard AND-EXOR logic minimizer; both result in Boolean networks with good testability attribute. It could be noted that an AND-OR-EXOR type logic network does not exist for the positive phase of this unique class of logic function. Experimental results report significant savings in all the power consumption components for designs based on standard cells pertaining to a 130nm UMC CMOS process The simulations have been extended to validate the savings across all three library corners (typical, best and worst case specifications).
Abstract: The Sensor Network consists of densely deployed
sensor nodes. Energy optimization is one of the most important
aspects of sensor application design. Data acquisition and aggregation
techniques for processing data in-network should be energy efficient.
Due to the cross-layer design, resource-limited and noisy nature
of Wireless Sensor Networks(WSNs), it is challenging to study
the performance of these systems in a realistic setting. In this
paper, we propose optimizing queries by aggregation of data and
data redundancy to reduce energy consumption without requiring
all sensed data and directed diffusion communication paradigm to
achieve power savings, robust communication and processing data
in-network. To estimate the per-node power consumption POWERTossim
mica2 energy model is used, which provides scalable and
accurate results. The performance analysis shows that the proposed
methods overcomes the existing methods in the aspects of energy
consumption in wireless sensor networks.
Abstract: The main aim of this work is to establish the
capabilities of new green buildings to ascertain off-grid electricity
generation based on the integration of wind turbines in the
conceptual model of a rotating tower [2] in Dubai. An in depth
performance analysis of the WinWind 3.0MW [3] wind turbine is
performed. Data based on the Dubai Meteorological Services is
collected and analyzed in conjunction with the performance analysis
of this wind turbine. The mathematical model is compared with
Computational Fluid Dynamics (CFD) results based on a conceptual
rotating tower design model. The comparison results are further
validated and verified for accuracy by conducting experiments on a
scaled prototype of the tower design. The study concluded that
integrating wind turbines inside a rotating tower can generate enough
electricity to meet the required power consumption of the building,
which equates to a wind farm containing 9 horizontal axis wind
turbines located at an approximate area of 3,237,485 m2 [14].
Abstract: This paper study the segmented split capacitor
Digital-to-Analog Converter (DAC) implemented in a differentialtype
12-bit Successive Approximation Analog-to-Digital Converter
(SA-ADC). The series capacitance split array method employed as it
reduced the total area of the capacitors required for high resolution
DACs. A 12-bit regular binary array structure requires 2049 unit
capacitors (Cs) while the split array needs 127 unit Cs. These results
in the reduction of the total capacitance and power consumption of
the series split array architectures as to regular binary-weighted
structures. The paper will show the 12-bit DAC series split capacitor
with 4-bit thermometer coded DAC architectures as well as the
simulation and measured results.
Abstract: The effects of ethylene (C2H4) feed position and
O2/C2H4 feed molar ratio on ethylene epoxidation in a parallel
dielectric barrier discharge (DBD) were studied. The results showed
that the ethylene feed position fraction of 0.5 and the feed molar
ratio of O2/C2H4 of 0.2:1 gave the highest EO selectivity of 34.3%
and the highest EO yield of 5.28% with low power consumptions of
2.11×10-16 Ws/molecule of ethylene converted and 6.34×10-16
Ws/molecule of EO produced when the DBD system was operated
under the best conditions: an applied voltage of 19 kV, an input
frequency of 500 Hz and a total feed flow rate of 50 cm3/min. The
separate ethylene feed system provided much higher epoxidation
activity as compared to the mixed feed system which gave EO
selectivity of 15.5%, EO yield of 2.1% and the power consumption of
EO produced of 7.7×10-16 Ws/molecule.
Abstract: The most widely used semiconductor memory types
are the Dynamic Random Access Memory (DRAM) and Static
Random Access memory (SRAM). Competition among memory
manufacturers drives the need to decrease power consumption and
reduce the probability of read failure. A technology that is relatively
new and has not been explored is the FinFET technology. In this
paper, a single cell Schmitt Trigger Based Static RAM using FinFET
technology is proposed and analyzed. The accuracy of the result is
validated by means of HSPICE simulations with 32nm FinFET
technology and the results are then compared with 6T SRAM using
the same technology.
Abstract: Fully customized hardware based technology provides high performance and low power consumption by specializing the tasks in hardware but lacks design flexibility since any kind of changes require re-design and re-fabrication. Software based solutions operate with software instructions due to which a great flexibility is achieved from the easy development and maintenance of the software code. But this execution of instructions introduces a high overhead in performance and area consumption. In past few decades the reconfigurable computing domain has been introduced which overcomes the traditional trades-off between flexibility and performance and is able to achieve high performance while maintaining a good flexibility. The dramatic gains in terms of chip performance and design flexibility achieved through the reconfigurable computing systems are greatly dependent on the design of their computational units being integrated with reconfigurable logic resources. The computational unit of any reconfigurable system plays vital role in defining its strength. In this research paper an RFU based computational unit design has been presented using the tightly coupled, multi-threaded reconfigurable cores. The proposed design has been simulated for VLIW based architectures and a high gain in performance has been observed as compared to the conventional computing systems.