Abstract: In many applications retransmissions of lost packets are not permitted. OFDM is a multi-carrier modulation scheme having excellent performance which allows overlapping in frequency domain. With OFDM there is a simple way of dealing with multipath relatively simple DSP algorithms.
In this paper, an image frame is compressed using DWT, and the compressed data is arranged in data vectors, each with equal number of coefficients. These vectors are quantized and binary coded to get the bit steams, which are then packetized and intelligently mapped to the OFDM system. Based on one-bit channel state information at the transmitter, the descriptions in order of descending priority are assigned to the currently good channels such that poorer sub-channels can only affect the lesser important data vectors. We consider only one-bit channel state information available at the transmitter, informing only about the sub-channels to be good or bad. For a good sub-channel, instantaneous received power should be greater than a threshold Pth. Otherwise, the sub-channel is in fading state and considered bad for that batch of coefficients. In order to reduce the system power consumption, the mapped descriptions onto the bad sub channels are dropped at the transmitter. The binary channel state information gives an opportunity to map the bit streams intelligently and to save a reasonable amount of power. By using MAT LAB simulation we can analysis the performance of our proposed scheme, in terms of system energy saving without compromising the received quality in terms of peak signal-noise ratio.
Abstract: This paper presents a 14-bit cyclic-pipelined Analog to digital converter (ADC) running at 1 MS/s. The architecture is based on a 1.5-bit per stage structure utilizing digital correction for each stage. The ADC consists of two 1.5-bit stages, one shift register delay line, and digital error correction logic. Inside each 1.5-bit stage, there is one gain-boosting op-amp and two comparators. The ADC was implemented in 0.18µm CMOS process and the design has an area of approximately 0.2 mm2. The ADC has a differential input range of 1.2 Vpp. The circuit has an average power consumption of 3.5mA with 10MHz sampling clocks. The post-layout simulations of the design satisfy 12-bit SNDR with a full-scale sinusoid input.
Abstract: In this paper, a low-power digital controller for DC-DC power conversion was presented. The controller generates the pulse-width modulated (PWM) signal from digital inputs provided by analog-to-digital converter (ADC). An efficient and simple design scheme to develop the control unit was discussed. This method allows minimization of the consumed resources of the chip and it is based on direct digital design approach. In this application, with the proposed scheme, nearly half area and two-third of the power consumption was saved compared to the conventional schemes. This work illustrates the possibility of implementing low-power and area-efficient power management circuit using direct digital design based approach.
Abstract: This paper presents a resonant-based read-out circuit for capacitive pressure sensors. The proposed read-out circuit consists of an LC oscillator and a counter. The circuit detects the capacitance changes of a capacitive pressure sensor by means of frequency shifts from its nominal operation frequency. The proposed circuit is designed in 0.18 m CMOS with an estimated power consumption of 43.1mW. Simulation results show that the circuit has a capacitive resolution of 8.06kHz/fF, which enables it for high resolution pressure detection.
Abstract: This paper aims to present the design, fabrication and test of a novel piezoelectric actuated, check-valves embedded micropump having the advantages of miniature size, light weight and low power consumption. This device is designed to pump gases and liquids with the capability of performing the self-priming and bubble-tolerant work mode by maximizing the stroke volume of the membrane as well as the compression ratio via minimization of the dead volume of the micropump chamber and channel. By experiment apparatus setup, we can get the real-time values of the flow rate of micropump, the displacement of the piezoelectric actuator and the deformation of the check valve, simultaneously. The micropump with check valve 0.4 mm in thickness obtained higher output performance under the sinusoidal waveform of 120 Vpp. The micropump achieved the maximum pumping rates of 42.2 ml/min and back pressure of 14.0 kPa at the corresponding frequency of 28 and 20 Hz. The presented micropump is able to pump gases with a pumping rate of 196 ml/min at operating frequencies of 280 Hz under the sinusoidal waveform of 120 Vpp.
Abstract: In this work we present a solution for DAGC (Digital
Automatic Gain Control) in WLAN receivers compatible to IEEE 802.11a/g standard. Those standards define communication in 5/2.4
GHz band using Orthogonal Frequency Division Multiplexing OFDM modulation scheme. WLAN Transceiver that we have used
enables gain control over Low Noise Amplifier (LNA) and a
Variable Gain Amplifier (VGA). The control over those signals is
performed in our digital baseband processor using dedicated hardware block DAGC. DAGC in this process is used to automatically control the VGA and LNA in order to achieve better
signal-to-noise ratio, decrease FER (Frame Error Rate) and hold the
average power of the baseband signal close to the desired set point.
DAGC function in baseband processor is done in few steps: measuring power levels of baseband samples of an RF signal,accumulating the differences between the measured power level and
actual gain setting, adjusting a gain factor of the accumulation, and
applying the adjusted gain factor the baseband values. Based on the measurement results of RSSI signal dependence to input power we have concluded that this digital AGC can be implemented applying
the simple linearization of the RSSI. This solution is very simple but also effective and reduces complexity and power consumption of the
DAGC. This DAGC is implemented and tested both in FPGA and in ASIC as a part of our WLAN baseband processor. Finally, we have integrated this circuit in a compact WLAN PCMCIA board based on MAC and baseband ASIC chips designed from us.
Abstract: A new approach has been used for optimized design of multipliers based upon the concepts of Vedic mathematics. The design has been targeted to state-of-the art field-programmable gate arrays (FPGAs). The multiplier generates partial products using Vedic mathematics method by employing basic 4x4 multipliers designed by exploiting 6-input LUTs and multiplexers in the same slices resulting in drastic reduction in area. The multiplier is realized on Xilinx FPGAs using devices Virtex-5 and Virtex-6.Carry Chain Adder was employed to obtain final products. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Booth, Carry Save, Carry ripple, and array multipliers. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power consumption.
Abstract: This paper presents the 20-GHz fractional PLL (Phase
Locked Loop) circuit for the next generation Wi-Fi by using 90 nm
TSMC process. The newly suggested millimeter wave 16/17
pre-scalar is designed and verified by measurement to make the
fractional PLL having a low quantization noise. The operational
bandwidth of the 60 GHz system is 15 % of the carrier frequency
which requires large value of Kv (VCO control gain) resulting in
degradation of phase noise. To solve this problem, this paper adopts
AFC (Automatic Frequency Controller) controlled 4-bit millimeter
wave VCO with small value of Kv. Also constant Kv is implemented
using 4-bit varactor bank. The measured operational bandwidth is 18.2
~ 23.2 GHz which is 25 % of the carrier frequency. The phase noise of
-58 and -96.2 dBc/Hz at 100 KHz and 1 MHz offset is measured
respectively. The total power consumption of the PLL is only 30 mW.
Abstract: In this paper, we present a cost-effective wireless
distributed load shedding system for non-emergency scenarios. In
power transformer locations where SCADA system cannot be used,
the proposed solution provides a reasonable alternative that combines
the use of microcontrollers and existing GSM infrastructure to send
early warning SMS messages to users advising them to proactively
reduce their power consumption before system capacity is reached
and systematic power shutdown takes place.
A novel communication protocol and message set have been
devised to handle the messaging between the transformer sites, where
the microcontrollers are located and where the measurements take
place, and the central processing site where the database server is
hosted. Moreover, the system sends warning messages to the endusers
mobile devices that are used as communication terminals. The
system has been implemented and tested via different experimental
results.
Abstract: This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on Instrumentation amplifier and it is useful for reducing offset In Wheatstone Bridge. The obtained gain is 645 with 1μv/°c Equivalent drift and 1.58mw power consumption. A Schmitt trigger and multiplexer circuit control output node. a high speed counter is designed in this work .the proposed circuit is designed and simulated In 0.18μm CMOS technology with 1.8v power supply.
Abstract: In this paper, the periodic surveillance scheme has
been proposed for any convex region using mobile wireless sensor
nodes. A sensor network typically consists of fixed number of
sensor nodes which report the measurements of sensed data such as
temperature, pressure, humidity, etc., of its immediate proximity
(the area within its sensing range). For the purpose of sensing an
area of interest, there are adequate number of fixed sensor
nodes required to cover the entire region of interest. It implies
that the number of fixed sensor nodes required to cover a given
area will depend on the sensing range of the sensor as well as
deployment strategies employed. It is assumed that the sensors to
be mobile within the region of surveillance, can be mounted on
moving bodies like robots or vehicle. Therefore, in our
scheme, the surveillance time period determines the number of
sensor nodes required to be deployed in the region of interest.
The proposed scheme comprises of three algorithms namely:
Hexagonalization, Clustering, and Scheduling, The first algorithm
partitions the coverage area into fixed sized hexagons that
approximate the sensing range (cell) of individual sensor node.
The clustering algorithm groups the cells into clusters, each of
which will be covered by a single sensor node. The later
determines a schedule for each sensor to serve its respective cluster.
Each sensor node traverses all the cells belonging to the cluster
assigned to it by oscillating between the first and the last cell for
the duration of its life time. Simulation results show that our
scheme provides full coverage within a given period of time using
few sensors with minimum movement, less power consumption,
and relatively less infrastructure cost.
Abstract: Flash memory has become an important storage device
in many embedded systems because of its high performance, low
power consumption and shock resistance. Multi-level cell (MLC) is
developed as an effective solution for reducing the cost and increasing
the storage density in recent years. However, most of flash file system
cannot handle the error correction sufficiently. To correct more errors
for MLC, we implement Reed-Solomon (RS) code to YAFFS, what is
widely used for flash-based file system. RS code has longer computing
time but the correcting ability is much higher than that of Hamming
code.
Abstract: Mostly the systems are dealing with time varying
signals. The Power efficiency can be achieved by adapting the system
activity according to the input signal variations. In this context
an adaptive rate filtering technique, based on the level crossing sampling
is devised. It adapts the sampling frequency and the filter order
by following the input signal local variations. Thus, it correlates the
processing activity with the signal variations. Interpolation is required
in the proposed technique. A drastic reduction in the interpolation
error is achieved by employing the symmetry during the interpolation
process. Processing error of the proposed technique is
calculated. The computational complexity of the proposed filtering
technique is deduced and compared to the classical one. Results
promise a significant gain of the computational efficiency and hence
of the power consumption.
Abstract: This paper examines the use of mechanical aerator for
oxidation-ditch process. The rotor, which controls the aeration, is the
main component of the aeration process. Therefore, the objective of
this study is to find out the variations in overall oxygen transfer
coefficient (KLa) and aeration efficiency (AE) for different
configurations of aerator by varying the parameters viz. speed of
aerator, depth of immersion, blade tip angles so as to yield higher
values of KLa and AE. Six different configurations of aerator were
developed and fabricated in the laboratory and were tested for abovementioned
parameters. The curved blade rotor (CBR) emerged as a
potential aerator with blade tip angle of 47°.
The mathematical models are developed for predicting the
behaviour of CBR w.r.t kLa and power. In laboratory studies, the
optimum value of KLa and AE were observed to be 10.33 h-1 and
2.269 kg O2/ kWh.
Abstract: This article proposes a current-mode square-rooting
circuit using current follower transconductance amplifier (CTFA).
The amplitude of the output current can be electronically controlled
via input bias current with wide input dynamic range. The proposed
circuit consists of only single CFTA. Without any matching
conditions and external passive elements, the circuit is then
appropriate for an IC architecture. The magnitude of the output signal
is temperature-insensitive. The PSpice simulation results are
depicted, and the given results agree well with the theoretical
anticipation. The power consumption is approximately 1.96mW at
±1.5V supply voltages.
Abstract: This paper proposes a method which reduces power consumption in single-error correcting, double error-detecting checker circuits that perform memory error correction code. Power is minimized with little or no impact on area and delay, using the degrees of freedom in selecting the parity check matrix of the error correcting codes. The genetic algorithm is employed to solve the non linear power optimization problem. The method is applied to two commonly used SEC-DED codes: standard Hamming and odd column weight Hsiao codes. Experiments were performed to show the performance of the proposed method.
Abstract: Full search block matching algorithm is widely used for hardware implementation of motion estimators in video compression algorithms. In this paper we are proposing a new architecture, which consists of a 2D parallel processing unit and a 1D unit both working in parallel. The proposed architecture reduces both data access power and computational power which are the main causes of power consumption in integer motion estimation. It also completes the operations with nearly the same number of clock cycles as compared to a 2D systolic array architecture. In this work sum of absolute difference (SAD)-the most repeated operation in block matching, is calculated in two steps. The first step is to calculate the SAD for alternate rows by a 2D parallel unit. If the SAD calculated by the parallel unit is less than the stored minimum SAD, the SAD of the remaining rows is calculated by the 1D unit. Early termination, which stops avoidable computations has been achieved with the help of alternate rows method proposed in this paper and by finding a low initial SAD value based on motion vector prediction. Data reuse has been applied to the reference blocks in the same search area which significantly reduced the memory access.
Abstract: Data security in u-Health system can be an important
issue because wireless network is vulnerable to hacking. However, it is
not easy to implement a proper security algorithm in an embedded
u-health monitoring because of hardware constraints such as low
performance, power consumption and limited memory size and etc. To
secure data that contain personal and biosignal information, we
implemented several security algorithms such as Blowfish, data
encryption standard (DES), advanced encryption standard (AES) and
Rivest Cipher 4 (RC4) for our u-Health monitoring system and the
results were successful. Under the same experimental conditions, we
compared these algorithms. RC4 had the fastest execution time.
Memory usage was the most efficient for DES. However, considering
performance and safety capability, however, we concluded that AES
was the most appropriate algorithm for a personal u-Health monitoring
system.
Abstract: This paper aims at to develop a robust optimization methodology for the mechatronic modules of machine tools by considering all important characteristics from all structural and control domains in one single process. The relationship between these two domains is strongly coupled. In order to reduce the disturbance caused by parameters in either one, the mechanical and controller design domains need to be integrated. Therefore, the concurrent integrated design method Design For Control (DFC), will be employed in this paper. In this connect, it is not only applied to achieve minimal power consumption but also enhance structural performance and system response at same time. To investigate the method for integrated optimization, a mechatronic feed drive system of the machine tools is used as a design platform. Pro/Engineer and AnSys are first used to build the 3D model to analyze and design structure parameters such as elastic deformation, nature frequency and component size, based on their effects and sensitivities to the structure. In addition, the robust controller,based on Quantitative Feedback Theory (QFT), will be applied to determine proper control parameters for the controller. Therefore, overall physical properties of the machine tool will be obtained in the initial stage. Finally, the technology of design for control will be carried out to modify the structural and control parameters to achieve overall system performance. Hence, the corresponding productivity is expected to be greatly improved.
Abstract: This study presents a simulation model for converting coal to methanol, based on gasification technology with the commercial chemical process simulator, Pro/II® V8.1.1. The methanol plant consists of air separation unit (ASU), gasification unit, gas clean-up unit, and methanol synthetic unit. The clean syngas is produced with the first three operating units, and the model has been verified with the reference data from United States Environment Protection Agency. The liquid phase methanol (LPMEOHTM) process is adopted in the methanol synthetic unit. Clean syngas goes through gas handing section to reach the reaction requirement, reactor loop/catalyst to generate methanol, and methanol distillation to get desired purity over 99.9 wt%. The ratio of the total energy combined with methanol and dimethyl ether to that of feed coal is 78.5% (gross efficiency). The net efficiency is 64.2% with the internal power consumption taken into account, based on the assumption that the efficiency of electricity generation is 40%.