Abstract: In recent years there has been renewal of interest in the
relation between Green IT and Cloud Computing. The growing use of
computers in cloud platform has caused marked energy consumption,
putting negative pressure on electricity cost of cloud data center. This
paper proposes an effective mechanism to reduce energy utilization in
cloud computing environments. We present initial work on the
integration of resource and power management that aims at reducing
power consumption. Our mechanism relies on recalling virtualization
services dynamically according to user-s virtualization request and
temporarily shutting down the physical machines after finish in order
to conserve energy. Given the estimated energy consumption, this
proposed effort has the potential to positively impact power
consumption. The results from the experiment concluded that energy
indeed can be saved by powering off the idling physical machines in
cloud platforms.
Abstract: This paper describes a CMOS four-quadrant
multiplier intended for use in the front-end receiver by utilizing the
square-law characteristic of the MOS transistor in the saturation
region. The circuit is based on 0.35 um CMOS technology simulated
using HSPICE software. The mixer has a third-order inter the power
consumption is 271uW from a single 1.2V power supply. One of the
features of the proposed design is using two MOS transistors
limitation to reduce the supply voltage, which leads to reduce the
power consumption. This technique provides a GHz bandwidth
response and low power consumption.
Abstract: Finite impulse response (FIR) filters have the advantage of linear phase, guaranteed stability, fewer finite precision errors, and efficient implementation. In contrast, they have a major disadvantage of high order need (more coefficients) than IIR counterpart with comparable performance. The high order demand imposes more hardware requirements, arithmetic operations, area usage, and power consumption when designing and fabricating the filter. Therefore, minimizing or reducing these parameters, is a major goal or target in digital filter design task. This paper presents an algorithm proposed for modifying values and the number of non-zero coefficients used to represent the FIR digital pulse shaping filter response. With this algorithm, the FIR filter frequency and phase response can be represented with a minimum number of non-zero coefficients. Therefore, reducing the arithmetic complexity needed to get the filter output. Consequently, the system characteristic i.e. power consumption, area usage, and processing time are also reduced. The proposed algorithm is more powerful when integrated with multiplierless algorithms such as distributed arithmetic (DA) in designing high order digital FIR filters. Here the DA usage eliminates the need for multipliers when implementing the multiply and accumulate unit (MAC) and the proposed algorithm will reduce the number of adders and addition operations needed through the minimization of the non-zero values coefficients to get the filter output.
Abstract: This paper presents a new circuit arrangement for a
current-mode Wheatstone bridge that is suitable for low-voltage
integrated circuits implementation. Compared to the other proposed
circuits, this circuit features severe reduction of the elements number,
low supply voltage (1V) and low power consumption (
Abstract: In this paper, a double balanced radio frequency multiplier
is presented which is customized for transmitted reference
ultra wideband (UWB) receivers. The multiplier uses 90nm model
parameters and exploits compensating transistors to provide controllable
gain for a Gilbert core. After performing periodic and quasiperiodic
non linear analyses the RF mixer (multiplier) achieves a
voltage conversion gain of 16 dB and a DSB noise figure of 8.253
dB with very low power consumption. A high degree of LO to RF
isolation (in the range of -94dB), RF to IF isolation (in the range of
-95dB) and LO to IF isolation (in the range of -143dB) is expected
for this design with an input-referred IP3 point of -1.93 dBm and an
input referred 1 dB compression point of -10.67dBm. The amount of
noise at the output is 7.7 nV/√Hz when the LO input is driven by
a 10dBm signal. The mixer manifests better results when compared
with other reported multiplier circuits and its Zero-IF performance
ensures its applicability as TR-UWB multipliers.
Abstract: As chip manufacturing technology is suddenly on the
threshold of major evaluation, which shrinks chip in size and
performance, LFSR (Linear Feedback Shift Register) is implemented
in layout level which develops the low power consumption chip,
using recent CMOS, sub-micrometer layout tools. Thus LFSR
counter can be a new trend setter in cryptography and is also
beneficial as compared to GRAY & BINARY counter and variety of
other applications.
This paper compares 3 architectures in terms of the hardware
implementation, CMOS layout and power consumption, using
Microwind CMOS layout tool. Thus it provides solution to a low
power architecture implementation of LFSR in CMOS VLSI.
Abstract: The problem of mapping tasks onto a computational grid with the aim to minimize the power consumption and the makespan subject to the constraints of deadlines and architectural requirements is considered in this paper. To solve this problem, we propose a solution from cooperative game theory based on the concept of Nash Bargaining Solution. The proposed game theoretical technique is compared against several traditional techniques. The experimental results show that when the deadline constraints are tight, the proposed technique achieves superior performance and reports competitive performance relative to the optimal solution.
Abstract: We consider a two-way relay network where two sources exchange information. A relay helps the two sources exchange information using the decode-and-XOR-forward protocol. We investigate the power minimization problem with minimum rate constraints. The system needs two time slots and in each time slot the required rate pair should be achievable. The power consumption is minimized in each time slot and we obtained the closed form solution. The simulation results confirm that the proposed power allocation scheme consumes lower total power than the conventional schemes.
Abstract: Power consumption is rapidly increased in data centers
because the number of data center is increased and more the scale of
data center become larger. Therefore, it is one of key research items to
reduce power consumption in data center. The peak power of a typical
server is around 250 watts. When a server is idle, it continues to use
around 60% of the power consumed when in use, though vendors are
putting effort into reducing this “idle" power load. Servers tend to
work at only around a 5% to 20% utilization rate, partly because of
response time concerns. An average of 10% of servers in their data
centers was unused. In those reason, we propose dynamic power
management system to reduce power consumption in green data
center. Experiment result shows that about 55% power consumption is
reduced at idle time.
Abstract: This paper describes a novel monitoring scheme to
minimize total active power in digital circuits depend on the demand
frequency, by adjusting automatically both supply voltage and
threshold voltages based on circuit operating conditions such as
temperature, process variations, and desirable frequency. The delay
monitoring results, will be control and apply so as to be maintained at
the minimum value at which the chip is able to operate for a given
clock frequency. Design details of power monitor are examined using
simulation framework in 32nm BTPM model CMOS process.
Experimental results show the overhead of proposed circuit in terms
of its power consumption is about 40 μW for 32nm technology;
moreover the results show that our proposed circuit design is not far
sensitive to the temperature variations and also process variations.
Besides, uses the simple blocks which offer good sensitivity, high
speed, the continuously feedback loop. This design provides up to
40% reduction in power consumption in active mode.
Abstract: With the advantage of wireless network technology,
there are a variety of mobile applications which make the issue of
wireless sensor networks as a popular research area in recent years.
As the wireless sensor network nodes move arbitrarily with the
topology fast change feature, mobile nodes are often confronted with
the void issue which will initiate packet losing, retransmitting,
rerouting, additional transmission cost and power consumption.
When transmitting packets, we would not predict void problem
occurring in advance. Thus, how to improve geographic routing with
void avoidance in wireless networks becomes an important issue. In
this paper, we proposed a greedy geographical void routing algorithm
to solve the void problem for wireless sensor networks. We use the
information of source node and void area to draw two tangents to
form a fan range of the existence void which can announce voidavoiding
message. Then we use source and destination nodes to draw
a line with an angle of the fan range to select the next forwarding
neighbor node for routing. In a dynamic wireless sensor network
environment, the proposed greedy void avoiding algorithm can be
more time-saving and more efficient to forward packets, and improve
current geographical void problem of wireless sensor networks.
Abstract: Electromagnetic interference (EMI) is one of the
serious problems in most electrical and electronic appliances
including fluorescent lamps. The electronic ballast used to regulate
the power flow through the lamp is the major cause for EMI. The
interference is because of the high frequency switching operation of
the ballast. Formerly, some EMI mitigation techniques were in
practice, but they were not satisfactory because of the hardware
complexity in the circuit design, increased parasitic components and
power consumption and so on. The majority of the researchers have
their spotlight only on EMI mitigation without considering the other
constraints such as cost, effective operation of the equipment etc. In
this paper, we propose a technique for EMI mitigation in fluorescent
lamps by integrating Frequency Modulation and Evolutionary
Programming. By the Frequency Modulation technique, the
switching at a single central frequency is extended to a range of
frequencies, and so, the power is distributed throughout the range of
frequencies leading to EMI mitigation. But in order to meet the
operating frequency of the ballast and the operating power of the
fluorescent lamps, an optimal modulation index is necessary for
Frequency Modulation. The optimal modulation index is determined
using Evolutionary Programming. Thereby, the proposed technique
mitigates the EMI to a satisfactory level without disturbing the
operation of the fluorescent lamp.
Abstract: Continuous-time delta-sigma analog digital converter (ADC) for radio frequency identification (RFID) complementary metal oxide semiconductor (CMOS) biosensor has been reported. This delta-sigma ADC is suitable for digital conversion of biosensor signal because of small process variation, and variable input range. As the input range of continuous-time switched current delta-sigma ADC (Dynamic range : 50 dB) can be limited by using current reference, amplification of biosensor signal is unnecessary. The input range is switched to wide input range mode or narrow input range mode by command of current reference. When the narrow input range mode, the input range becomes ± 0.8 V. The measured power consumption is 5 mW and chip area is 0.31 mm^2 using 1.2 um standard CMOS process. Additionally, automatic input range detecting system is proposed because of RFID biosensor applications.
Abstract: The importance of low power consumption is widely
acknowledged due to the increasing use of portable devices, which
require minimizing the consumption of energy. Energy dissipation is
heavily dependent on the software used in the system. Applying
design patterns in object-oriented designs is a common practice
nowadays. In this paper we analyze six design patterns and explore
the effect of them on energy consumption and performance.
Abstract: With data centers, end-users can realize the pervasiveness of services that will be one day the cornerstone of our lives. However, data centers are often classified as computing systems that consume the most amounts of power. To circumvent such a problem, we propose a self-adaptive weighted sum methodology that jointly optimizes the performance and power consumption of any given data center. Compared to traditional methodologies for multi-objective optimization problems, the proposed self-adaptive weighted sum technique does not rely on a systematical change of weights during the optimization procedure. The proposed technique is compared with the greedy and LR heuristics for large-scale problems, and the optimal solution for small-scale problems implemented in LINDO. the experimental results revealed that the proposed selfadaptive weighted sum technique outperforms both of the heuristics and projects a competitive performance compared to the optimal solution.
Abstract: Link reliability and transmitted power are two important design constraints in wireless network design. Error control coding (ECC) is a classic approach used to increase link reliability and to lower the required transmitted power. It provides coding gain, resulting in transmitter energy savings at the cost of added decoder power consumption. But the choice of ECC is very critical in the case of wireless sensor network (WSN). Since the WSNs are energy constraint in nature, both the BER and power consumption has to be taken into count. This paper develops a step by step approach in finding suitable error control codes for WSNs. Several simulations are taken considering different error control codes and the result shows that the RS(31,21) fits both in BER and power consumption criteria.
Abstract: In this paper, to resolve the problem of existing
schemes, an alternative fast handover Proxy Mobile IPv6 (PMIPv6)
scheme using the IEEE 802.21 Media Independent Handover (MIH)
function is proposed for heterogeneous wireless networks. The proposed
scheme comes to support fast handover for the mobile node
(MN) irrespective of the presence or absence of MIH functionality
as well as L3 mobility functionality, whereas the MN in existing
schemes has to implement MIH functionality. That is, the proposed
scheme does not require the MN to be involved in MIH related signaling
required for handover procedure. The base station (BS) with MIH
functionality performs handover on behalf of the MN. Therefore, the
proposed scheme can reduce burden and power consumption of MNs
with limited resource and battery power since MNs are not required
to be involved for the handover procedure. In addition, the proposed
scheme can reduce considerably traffic overhead over wireless links
between MN and BS since signaling messages are reduced.
Abstract: The power consumption of an Optical Packet Switch
equipped with SOA technology based Spanke switching fabric is
evaluated. Sophisticated analytical models are introduced to evaluate
the power consumption versus the offered traffic, the main
switch parameters, and the used device characteristics. The impact
of Amplifier Spontaneous Emission (ASE) noise generated by a
transmission system on the power consumption is investigated. As
a matter of example for 32×32 switches supporting 64 wavelengths
and offered traffic equal to 0,8, the average energy consumption per
bit is 5, 07 · 10-2 nJ/bit and increases if ASE noise introduced by
the transmission systems is increased.
Abstract: In this paper, we proposed an efficient data
compression strategy exploiting the multi-resolution characteristic of
the wavelet transform. We have developed a sensor node called
“Smart Sensor Node; SSN". The main goals of the SSN design are
lightweight, minimal power consumption, modular design and robust
circuitry. The SSN is made up of four basic components which are a
sensing unit, a processing unit, a transceiver unit and a power unit.
FiOStd evaluation board is chosen as the main controller of the SSN
for its low costs and high performance. The software coding of the
implementation was done using Simulink model and MATLAB
programming language. The experimental results show that the
proposed data compression technique yields recover signal with good
quality. This technique can be applied to compress the collected data
to reduce the data communication as well as the energy consumption
of the sensor and so the lifetime of sensor node can be extended.
Abstract: This paper presents a methodology towards the emulation of the electrical power consumption of the RF device during the cellular phone/handset transmission mode using the LTE technology. The emulation methodology takes the physical environmental variables and the logical interface between the baseband and the RF system as inputs to compute the emulated power dissipation of the RF device. The emulated power, in between the measured points corresponding to the discrete values of the logical interface parameters is computed as a polynomial interpolation using polynomial basis functions. The evaluation of polynomial and spline curve fitting models showed a respective divergence (test error) of 8% and 0.02% from the physically measured power consumption. The precisions of the instruments used for the physical measurements have been modeled as intervals. We have been able to model the power consumption of the RF device operating at 5MHz using homotopy between 2 continuous power consumptions of the RF device operating at the bandwidths 3MHz and 10MHz.