Abstract: This paper deals with the study of interest in the fields
of Steganography and Steganalysis. Steganography involves hiding
information in a cover media to obtain the stego media in such a
way that the cover media is perceived not to have any embedded
message for its unintended recipients. Steganalysis is the mechanism
of detecting the presence of hidden information in the stego media
and it can lead to the prevention of disastrous security incidents. In
this paper, we provide a critical review of the steganalysis algorithms
available to analyze the characteristics of an image stego media
against the corresponding cover media and understand the process
of embedding the information and its detection. We anticipate that
this paper can also give a clear picture of the current trends in
steganography so that we can develop and improvise appropriate
steganalysis algorithms.
Abstract: According to the rules of quantum mechanics there is a non-vanishing probability of for an electron to tunnel through a thin insulating barrier or a thin capacitor which is not possible according to the laws of classical physics. Tunneling of electron through a thin insulating barrier or tunnel junction is a random event and the magnitude of current flowing due to the tunneling of electron is very low. As the current flowing through a Single Electron Transistor (SET) is the result of electron tunneling through tunnel junctions of its source and drain the supply voltage requirement is also very low. As a result, the power consumption across a Single Electron Transistor is ultra-low in comparison to that of a MOSFET. In this paper simulations have been done with PSPICE for an inverter built with both SETs and MOSFETs. 35mV supply voltage was used for a SET built inverter circuit and the supply voltage used for a CMOS inverter was 3.5V.
Abstract: In a conventional network, most network devices, such as routers, are dedicated devices that do not have much variation in capacity. In recent years, a new concept of network functions virtualisation (NFV) has come into use. The intention is to implement a variety of network functions with software on general-purpose servers and this allows the network operator to select their capacities and locations without any constraints. This paper focuses on the allocation of NFV-based routing functions which are one of critical network functions, and presents the virtual routing function allocation algorithm that minimizes the total power consumption. In addition, this study presents the useful allocation policy of virtual routing functions, based on an evaluation with a ladder-shaped network model. This policy takes the ratio of the power consumption of a routing function to that of a circuit and traffic distribution between areas into consideration. Furthermore, the present paper shows that there are cases where the use of NFV-based routing functions makes it possible to reduce the total power consumption dramatically, in comparison to a conventional network, in which it is not economically viable to distribute small-capacity routing functions.
Abstract: The United Arab Emirates (UAE) is significantly dependent on desalinated water and groundwater resource, which is expensive and highly energy intensive. Despite the scarce water resource, stagnates only 54% of the recycled water was reused in 2012, and due to the lack of infrastructure to reuse the recycled water, the portion is expected to decrease with growing water usage. In this study, an “Oasis” complex comprised of Sustainable Farming Compartments (SFC) was proposed for reusing treated wastewater. The wastewater is used to decrease the ambient temperature of the SFC via an evaporative cooler. The SFC prototype was designed, built, and tested in an environmentally controlled laboratory and field site to evaluate the feasibility and effectiveness of the SFC subjected to various climatic conditions in Abu Dhabi. Based on the experimental results, the temperature drop achieved in the SFC in the laboratory and field site were5 ̊C from 22 ̊C and 7- 15 ̊C (from 33-45 ̊C to average 28 ̊C at relative humidity < 50%), respectively. An energy simulation using TRNSYS was performed to extend and validate the results obtained from the experiment. The results from the energy simulation and experiments show statistically close agreement. The total power consumption of the SFC system was approximately three and a half times lower than that of an electrical air conditioner. Therefore, by using treated wastewater, the SFC has a promising prospect to solve Abu Dhabi’s ecological concern related to desertification and wind erosion.
Abstract: In this paper, dynamic comparator structure employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters have been presented. The proposed comparator has low consumption thanks to power reduction methods. They have the ability for offset adjustment. The comparator consumes 14.3 μW at 100 MHz which is equal to 11.8 fJ. The comparator has been designed and simulated in 180 nm CMOS. Layouts occupy 210 μm2.
Abstract: Ubiquity of natural disasters during last few decades
have risen serious questions towards the prediction of such events
and human safety. Every disaster regardless its proportion has a
precursor which is manifested as a disruption of some environmental
parameter such as temperature, humidity, pressure, vibrations and
etc. In order to anticipate and monitor those changes, in this paper
we propose an overall system for disaster prediction and monitoring,
based on wireless sensor network (WSN). Furthermore, we introduce
a modified and simplified WSN routing protocol built on the top
of the trickle routing algorithm. Routing algorithm was deployed
using the bluetooth low energy protocol in order to achieve low
power consumption. Performance of the WSN network was analyzed
using a real life system implementation. Estimates of the WSN
parameters such as battery life time, network size and packet delay are
determined. Based on the performance of the WSN network, proposed
system can be utilized for disaster monitoring and prediction due to
its low power profile and mesh routing feature.
Abstract: In this paper, a low voltage high performance current mirror is presented. Its most important specifications, which are improved in this work, are analyzed and formulated proving that it has such outstanding merits as: Very low input resistance of 26mΩ, very wide current dynamic range of 8 decades from 10pA to 1mA (160dB) together with an extremely low current copy error of less than 0.6ppm, and very low input and output voltages. Furthermore, the proposed current mirror bandwidth is 944MHz utilizing very low power consumption (267μW) and transistors count. HSPICE simulation results are performed using TSMC 0.18μm CMOS technology utilizing 1.8V single power supply, confirming the theoretically proved outstanding performance of the proposed current mirror. Monte Carlo simulation of its most important parameter is also examined showing its sufficiently resistance against technology process variations.
Abstract: This paper presents a digital non-linear pulse-width modulation (PWM) controller in a high-voltage (HV) buck-boost DC-DC converter for the piezoelectric transducer of the down-hole acoustic telemetry system. The proposed design controls the generation of output signal with voltage higher than the supply voltage and is targeted to work under high temperature. To minimize the power consumption and silicon area, a simple and efficient design scheme is employed to develop the PWM controller. The proposed PWM controller consists of serial to parallel (S2P) converter, data assign block, a mode and duty cycle controller (MDC), linearly PWM (LPWM) and noise shaper, pulse generator and clock generator. To improve the reliability of circuit operation at higher temperature, this design is fabricated with the 1.0-μm silicon-on-insulator (SOI) CMOS process. The implementation results validated that the proposed design has the advantages of smaller size, lower power consumption and robust thermal stability.
Abstract: An innovative approach to develop modified scaling free CORDIC based two parallel pipelined Multipath Delay Commutator (MDC) FFT and IFFT architectures for radix 22 FFT algorithm is presented. Multipliers and adders are the most important data paths in FFT and IFFT architectures. Multipliers occupy high area and consume more power. In order to optimize the area and power overhead, modified scaling-free CORDIC based complex multiplier is utilized in the proposed design. In general twiddle factor values are stored in RAM block. In the proposed work, modified scaling-free CORDIC based twiddle factor generator unit is used to generate the twiddle factor and efficient switching units are used. In addition to this, four point FFT operations are performed without complex multiplication which helps to reduce area and power in the last two stages of the pipelined architectures. The design proposed in this paper is based on multipath delay commutator method. The proposed design can be extended to any radix 2n based FFT/IFFT algorithm to improve the throughput. The work is synthesized using Synopsys design Compiler using TSMC 90-nm library. The proposed method proves to be better compared to the reference design in terms of area, throughput and power consumption. The comparative analysis of the proposed design with Xilinx FPGA platform is also discussed in the paper.
Abstract: Interaction between mixing and crystallization is often
ignored despite the fact that it affects almost every aspect of the
operation including nucleation, growth, and maintenance of the
crystal slurry. This is especially pronounced in multiple impeller
systems where flow complexity is increased. By choosing proper
mixing parameters, what closely depends on the knowledge of the
hydrodynamics in a mixing vessel, the process of batch cooling
crystallization may considerably be improved. The values that render
useful information when making this choice are mixing time and
power consumption. The predominant motivation for this work was
to investigate the extent to which radial dual impeller configuration
influences mixing time, power consumption and consequently the
values of metastable zone width and nucleation rate. In this research,
crystallization of borax was conducted in a 15 dm3 baffled batch
cooling crystallizer with an aspect ratio (H/T) of 1.3. Mixing was
performed using two straight blade turbines (4-SBT) mounted on the
same shaft that generated radial fluid flow. Experiments were
conducted at different values of N/NJS ratio (impeller speed/
minimum impeller speed for complete suspension), D/T ratio
(impeller diameter/crystallizer diameter), c/D ratio (lower impeller
off-bottom clearance/impeller diameter), and s/D ratio (spacing
between impellers/impeller diameter). Mother liquor was saturated at
30°C and was cooled at the rate of 6°C/h. Its concentration was
monitored in line by Na-ion selective electrode. From the values of
supersaturation that was monitored continuously over process time, it
was possible to determine the metastable zone width and
subsequently the nucleation rate using the Mersmann’s nucleation
criterion. For all applied dual impeller configurations, the mixing
time was determined by potentiometric method using a pulse
technique, while the power consumption was determined using a
torque meter produced by Himmelstein & Co. Results obtained in
this investigation show that dual impeller configuration significantly
influences the values of mixing time, power consumption as well as
the metastable zone width and nucleation rate. A special attention
should be addressed to the impeller spacing considering the flow
interaction that could be more or less pronounced depending on the
spacing value.
Abstract: While the feature sizes of recent Complementary Metal
Oxid Semiconductor (CMOS) devices decrease the influence of static
power prevails their energy consumption. Thus, power savings that
benefit from Dynamic Frequency and Voltage Scaling (DVFS) are
diminishing and temporal shutdown of cores or other microchip
components become more worthwhile. A consequence of powering off unused parts of a chip is that the
relative difference between idle and fully loaded power consumption
is increased. That means, future chips and whole server systems gain
more power saving potential through power-aware load balancing,
whereas in former times this power saving approach had only
limited effect, and thus, was not widely adopted. While powering
off complete servers was used to save energy, it will be superfluous
in many cases when cores can be powered down. An important
advantage that comes with that is a largely reduced time to respond
to increased computational demand. We include the above developments in a server power model
and quantify the advantage. Our conclusion is that strategies from
datacenters when to power off server systems might be used in the
future on core level, while load balancing mechanisms previously
used at core level might be used in the future at server level.
Abstract: Many cluster based routing protocols have been
proposed in the field of wireless sensor networks, in which a group of
nodes are formed as clusters. A cluster head is selected from one
among those nodes based on residual energy, coverage area, number
of hops and that cluster-head will perform data gathering from
various sensor nodes and forwards aggregated data to the base station
or to a relay node (another cluster-head), which will forward the
packet along with its own data packet to the base station. Here a
Game Theory based Diligent Energy Utilization Algorithm (GTDEA)
for routing is proposed. In GTDEA, the cluster head selection is done
with the help of game theory, a decision making process, that selects
a cluster-head based on three parameters such as residual energy
(RE), Received Signal Strength Index (RSSI) and Packet Reception
Rate (PRR). Finding a feasible path to the destination with minimum
utilization of available energy improves the network lifetime and is
achieved by the proposed approach. In GTDEA, the packets are
forwarded to the base station using inter-cluster routing technique,
which will further forward it to the base station. Simulation results
reveal that GTDEA improves the network performance in terms of
throughput, lifetime, and power consumption.
Abstract: Wireless Sensor Networks (WSNs), which sense
environmental data with battery-powered nodes, require multi-hop
communication. This power-demanding task adds an extra workload
that is unfairly distributed across the network. As a result, nodes run
out of battery at different times: this requires an impractical
individual node maintenance scheme. Therefore we investigate a new
Cooperative Sensing approach that extends the WSN operational life
and allows a more practical network maintenance scheme (where all
nodes deplete their batteries almost at the same time). We propose a
novel cooperative algorithm that derives a piecewise representation
of the sensed signal while controlling approximation accuracy.
Simulations show that our algorithm increases WSN operational life
and spreads communication workload evenly. Results convey a
counterintuitive conclusion: distributing workload fairly amongst
nodes may not decrease the network power consumption and yet
extend the WSN operational life. This is achieved as our cooperative
approach decreases the workload of the most burdened cluster in the
network.
Abstract: In this paper, a novel Linear Feedback Shift Register
(LFSR) with Look Ahead Clock Gating (LACG) technique is
presented to reduce the power consumption in modern processors
and System-on-Chip. Clock gating is a predominant technique used
to reduce unwanted switching of clock signals. Several clock gating
techniques to reduce the dynamic power have been developed, of
which LACG is predominant. LACG computes the clock enabling
signals of each flip-flop (FF) one cycle ahead of time, based on the
present cycle data of the flip-flops on which it depends. It overcomes
the timing problems in the existing clock gating methods like datadriven
clock gating and Auto-Gated flip-flops (AGFF) by allotting a
full clock cycle for the determination of the clock enabling signals.
Further to reduce the power consumption in LACG technique, FFs
can be grouped so that they share a common clock enabling signal.
Simulation results show that the novel grouped LFSR with LACG
achieves 15.03% power savings than conventional LFSR with LACG
and 44.87% than data-driven clock gating.
Abstract: Maintaining factory default battery endurance rate
over time in supporting huge amount of running applications on
energy-restricted mobile devices has created a new challenge for
mobile applications developer. While delivering customers’
unlimited expectations, developers are barely aware of efficient use
of energy from the application itself. Thus, developers need a set of
valid energy consumption indicators in assisting them to develop
energy saving applications. In this paper, we present a few software
product metrics that can be used as an indicator to measure energy
consumption of Android-based mobile applications in the early of
design stage. In particular, Trepn Profiler (Power profiling tool for
Qualcomm processor) has used to collect the data of mobile
application power consumption, and then analyzed for the 23
software metrics in this preliminary study. The results show that
McCabe cyclomatic complexity, number of parameters, nested block
depth, number of methods, weighted methods per class, number of
classes, total lines of code and method lines have direct relationship
with power consumption of mobile application.
Abstract: Processing of high-silicon bauxite on the base of the
traditional clinkering method is related to high power consumption
and capital investments, which makes production of alumina from
those ores non-competitive in terms of basic economic showings. For
these reasons, development of technological solutions enabling to
process bauxites with various chemical and mineralogical structures
efficiently with low level of thermal power consumption is important.
Flow sheet of the studies on washability of ores from the Timanskoe
and the Severo-Onezhskoe deposits is on the base of the flotation
method.
Abstract: The main issue in designing a wireless sensor network
(WSN) is the finding of a proper routing protocol that complies with
the several requirements of high reliability, short latency, scalability,
low power consumption, and many others. This paper proposes a
novel routing algorithm that complies with these design
requirements. The new routing protocol divides the WSN into several subnetworks
and each sub-network is divided into several clusters. This
division is designed to reduce the number of radio transmission and
hence decreases the power consumption. The network division may
be changed dynamically to adapt with the network changes and
allows the realization of the design requirements.
Abstract: A novel design technique employing CMOS Current
Feedback Operational Amplifier (CFOA) is presented. The feature of
consumption very low power in designing pseudo-OTA is used to
decreasing the total power consumption of the proposed CFOA. This
design approach applies pseudo-OTA as input stage cascaded with
buffer stage. Moreover, the DC input offset voltage and harmonic
distortion (HD) of the proposed CFOA are very low values compared
with the conventional CMOS CFOA due to the symmetrical input
stage. P-Spice simulation results are obtained using 0.18μm MIETEC
CMOS process parameters and supply voltage of ±1.2V, 50μA
biasing current. The p-spice simulation shows excellent improvement
of the proposed CFOA over existing CMOS CFOA. Some of these
performance parameters, for example, are DC gain of 62. dB, openloop
gain bandwidth product of 108 MHz, slew rate (SR+) of
+71.2V/μS, THD of -63dB and DC consumption power (PC) of
2mW.
Abstract: This paper describes an optimization tool-based
design strategy for a Current Mode Logic CML divide-by-2 circuit.
Representing a building block for output frequency generation in a
RFID protocol based-frequency synthesizer, the circuit was designed
to minimize the power consumption for driving of multiple loads
with unbalancing (at transceiver level). Implemented with XFAB
XC08 180 nm technology, the circuit was optimized through
MunEDA WiCkeD tool at Cadence Virtuoso Analog Design
Environment ADE.
Abstract: This paper is part of a study to develop robots for
farming. As such power requirement to operate equipment attach to
such robots become an important factor. Soil-tool interaction plays
major role in power consumption, thus predicting accurately the
forces which act on the blade during the farming is very important for
optimal designing of farm equipment. In this paper, a finite element
investigation for tillage tools and soil interaction is described by
using an inelastic constitutive material law for agriculture
application. A 3-dimensional (3D) nonlinear finite element analysis
(FEA) is developed to examine behavior of a blade with different
rake angles moving in a block of soil, and to estimate the blade force.
The soil model considered is an elastic-plastic with non-associated
Drucker-Prager material model. Special use of contact elements are
employed to consider connection between soil-blade and soil-soil
surfaces. The FEA results are compared with experimental ones,
which show good agreement in accurately predicting draft forces
developed on the blade when it moves through the soil. Also a very
good correlation was obtained between FEA results and analytical
results from classical soil mechanics theories for straight blades.
These comparisons verified the FEA model developed. For analyzing
complicated soil-tool interactions and for optimum design of blades,
this method will be useful.