Abstract: CNFET has emerged as an alternative material to
silicon for high performance, high stability and low power SRAM
design in recent years. SRAM functions as cache memory in
computers and many portable devices. In this paper, a new SRAM
cell design based on CNFET technology is proposed. The proposed
SRAM cell design for CNFET is compared with SRAM cell designs
implemented with the conventional CMOS and FinFET in terms of
speed, power consumption, stability, and leakage current. The
HSPICE simulation and analysis show that the dynamic power
consumption of the proposed 8T CNFET SRAM cell’s is reduced
about 48% and the SNM is widened up to 56% compared to the
conventional CMOS SRAM structure at the expense of 2% leakage
power and 3% write delay increase.
Abstract: In this paper we use low frequency noise analysis to understand and map the current conduction path in a multi gate junctionless FinFET. The device used in this study behaves as a gated resistor and shows excellent short channel effect suppression due to its multi gate structure. Generally for a bulk conduction device like the junctionless device studied in this work, the low frequency noise can be modelled using the mobility fluctuation model; however for this device we can also see the effect of carrier fluctuations on the LFN characteristic. The noise characteristic at different gate bias and also the possible location of the traps is explained.
Abstract: In this paper, FinFET devices are analyzed with
emphasis on sub-threshold leakage current control. This is achieved
through proper biasing of the back gate, and through the use of
asymmetric work functions for the four terminal FinFET devices. We
are also examining different configurations of multiplexers and XOR
gates using transistors of symmetric and asymmetric work functions.
Based on extensive characterization data for MUX circuits, our
proposed configuration using symmetric devices lead to leakage
current and delay improvements of 65% and 47% respectively
compared to results in the literature. For XOR gates, a 90%
improvement in the average leakage current is achieved by using
asymmetric devices. All simulations are based on a 25nm FinFET
technology using the University of Florida UFDG model.
Abstract: In this paper, we have proposed a novel FinFET with
extended body under the poly gate, which is called EB-FinFET, and
its characteristic is demonstrated by using three-dimensional (3-D)
numerical simulation. We have analyzed and compared it with
conventional FinFET. The extended body height dependence on the
drain induced barrier lowering (DIBL) and subthreshold swing (S.S)
have been also investigated. According to the 3-D numerical
simulation, the proposed structure has a firm structure, an acceptable
short channel effect (SCE), a reduced series resistance, an increased
on state drain current (I
on) and a large normalized I
DS. Furthermore,
the structure can also improve corner effect and reduce self-heating
effect due to the extended body. Our results show that the EBFinFET
is excellent for nanoscale device.
Abstract: The most widely used semiconductor memory types
are the Dynamic Random Access Memory (DRAM) and Static
Random Access memory (SRAM). Competition among memory
manufacturers drives the need to decrease power consumption and
reduce the probability of read failure. A technology that is relatively
new and has not been explored is the FinFET technology. In this
paper, a single cell Schmitt Trigger Based Static RAM using FinFET
technology is proposed and analyzed. The accuracy of the result is
validated by means of HSPICE simulations with 32nm FinFET
technology and the results are then compared with 6T SRAM using
the same technology.