Low Frequency Noise Behavior of Independent Gate Junctionless FinFET
In this paper we use low frequency noise analysis to understand and map the current conduction path in a multi gate junctionless FinFET. The device used in this study behaves as a gated resistor and shows excellent short channel effect suppression due to its multi gate structure. Generally for a bulk conduction device like the junctionless device studied in this work, the low frequency noise can be modelled using the mobility fluctuation model; however for this device we can also see the effect of carrier fluctuations on the LFN characteristic. The noise characteristic at different gate bias and also the possible location of the traps is explained.
[1] C. Y. Chang, T. L. Lee, C. Wann, L. S. Lai, H. M. Chen, C. C. Yeh, C.
S. Chang, C. C. Ho, J. C. Sheu, T. M. Kwok, F. Yuan, S. M. Yu, C. F.
Hu, J. J. Shen, Y. H. Liu, C. P. Chen, S. C. Chen, L. S. Chen, L. Chen,
Y. H. Chiu, C.Y. Fu, M. J. Huang, Y. L. Huang, S. T. Hung, J. J. Liaw,
H. C. Lin, H. H. Lin, L. T. S. Lin, S. S. Lin, Y. J. Mii, E. Ou-Yang, M.
F. Shieh, C. C. Su, S. P. Tai, H. J. Tao, M. H. Tsai, K. T. Tseng, K. W.
Wang, S. B. Wang, J. J. Xu, F. K. Yang, S. T. Yang, C. N. Yeh, “A 25-
nm gate-lenth FinFET transistor module for 32nm node”, IEDM Tech.
Dig., 2009, pp. 1-4.
[2] S. Xin, L. Qiang, V. Moroz, H. Takeuchi, G. Gebara, J. Wetzel, S.
Ikeda, C. Shin, T.J.K. Liu, “Tri-Gate Bulk MOSFET Design for CMOS
Scaling to the End of the Roadmap”, IEEE Electron Device Lett., vol.
29, no.5, pp. 491-493, May 2008.
[3] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A.
Agarwal, C. H. tung, K. M. Hoe, S. R. Omanpuliyur, D. Tripathi, A. O.
Adeyeye, G. Q. Lo, N. Balasubtramanian and D. L. Kwong, “Ultra-
Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of
Diameter, Channel-Orientation and Low Temperature Device
Performance”, IEDM 2006, pp. 1-4.
[4] B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. Q. Lo and D. L
Kwong, “Vertical silicon-nanowire formation and gate-all-around
MOSFET”, IEEE Electron Device Lett, vol. 29, no. 7, pp. 791-794, Jul.
2008.
[5] T. Honda, M. Kawashima, Y. Sekine, K. Yamazoe, E. Sakamoto,
“Hyper-NA imaging in ArF immersion lithography”, Microprocesses
and Nanotechnology Conference 2005, pp. 10-11, 2005.
[6] J S. Borkar, “Design perspectives on 22nm CMOS and beyond”, IEDM
Tech. Dig., 2009, pp. 93-94.
[7] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain,
P. Razavi, B. O’neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy,
R. Murphy, “Nanowire transistors without junctions”, Nature
Nanotechnology, vol. 5, pp. 225-229, Feb. 2010.
[8] A.M. Ionescu, “Electronic Devices: Nanowire transistors made easy”,
Nature Nanotechnology, vol. 5, pp. 178-179, Mar. 2010.
[9] C. W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P.
Razavi, J. P. Colinge, “High-Temperature Performance of Silicon
Juntionless MOSFETs”, IEEE Tran. Electron Devices, vol. 57, no. 3, pp.
620-625, Mar. 2010.
[10] Dae-Young Jeon, “Low Frequency noise behavior of junctionless
transistors comared to inversion –mode transistors,” Solid-State
Electronics, vol. 81, 2013.
[1] C. Y. Chang, T. L. Lee, C. Wann, L. S. Lai, H. M. Chen, C. C. Yeh, C.
S. Chang, C. C. Ho, J. C. Sheu, T. M. Kwok, F. Yuan, S. M. Yu, C. F.
Hu, J. J. Shen, Y. H. Liu, C. P. Chen, S. C. Chen, L. S. Chen, L. Chen,
Y. H. Chiu, C.Y. Fu, M. J. Huang, Y. L. Huang, S. T. Hung, J. J. Liaw,
H. C. Lin, H. H. Lin, L. T. S. Lin, S. S. Lin, Y. J. Mii, E. Ou-Yang, M.
F. Shieh, C. C. Su, S. P. Tai, H. J. Tao, M. H. Tsai, K. T. Tseng, K. W.
Wang, S. B. Wang, J. J. Xu, F. K. Yang, S. T. Yang, C. N. Yeh, “A 25-
nm gate-lenth FinFET transistor module for 32nm node”, IEDM Tech.
Dig., 2009, pp. 1-4.
[2] S. Xin, L. Qiang, V. Moroz, H. Takeuchi, G. Gebara, J. Wetzel, S.
Ikeda, C. Shin, T.J.K. Liu, “Tri-Gate Bulk MOSFET Design for CMOS
Scaling to the End of the Roadmap”, IEEE Electron Device Lett., vol.
29, no.5, pp. 491-493, May 2008.
[3] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A.
Agarwal, C. H. tung, K. M. Hoe, S. R. Omanpuliyur, D. Tripathi, A. O.
Adeyeye, G. Q. Lo, N. Balasubtramanian and D. L. Kwong, “Ultra-
Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of
Diameter, Channel-Orientation and Low Temperature Device
Performance”, IEDM 2006, pp. 1-4.
[4] B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. Q. Lo and D. L
Kwong, “Vertical silicon-nanowire formation and gate-all-around
MOSFET”, IEEE Electron Device Lett, vol. 29, no. 7, pp. 791-794, Jul.
2008.
[5] T. Honda, M. Kawashima, Y. Sekine, K. Yamazoe, E. Sakamoto,
“Hyper-NA imaging in ArF immersion lithography”, Microprocesses
and Nanotechnology Conference 2005, pp. 10-11, 2005.
[6] J S. Borkar, “Design perspectives on 22nm CMOS and beyond”, IEDM
Tech. Dig., 2009, pp. 93-94.
[7] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain,
P. Razavi, B. O’neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy,
R. Murphy, “Nanowire transistors without junctions”, Nature
Nanotechnology, vol. 5, pp. 225-229, Feb. 2010.
[8] A.M. Ionescu, “Electronic Devices: Nanowire transistors made easy”,
Nature Nanotechnology, vol. 5, pp. 178-179, Mar. 2010.
[9] C. W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P.
Razavi, J. P. Colinge, “High-Temperature Performance of Silicon
Juntionless MOSFETs”, IEEE Tran. Electron Devices, vol. 57, no. 3, pp.
620-625, Mar. 2010.
[10] Dae-Young Jeon, “Low Frequency noise behavior of junctionless
transistors comared to inversion –mode transistors,” Solid-State
Electronics, vol. 81, 2013.
@article{"International Journal of Electrical, Electronic and Communication Sciences:65030", author = "A. Kamath and Z. X. Chen and C. J. Gu and F. Zheng and X. P. Wang and N. Singh and G-Q. Lo", title = "Low Frequency Noise Behavior of Independent Gate Junctionless FinFET", abstract = "In this paper we use low frequency noise analysis to understand and map the current conduction path in a multi gate junctionless FinFET. The device used in this study behaves as a gated resistor and shows excellent short channel effect suppression due to its multi gate structure. Generally for a bulk conduction device like the junctionless device studied in this work, the low frequency noise can be modelled using the mobility fluctuation model; however for this device we can also see the effect of carrier fluctuations on the LFN characteristic. The noise characteristic at different gate bias and also the possible location of the traps is explained.
", keywords = "LFN analysis, junctionless, Current conduction path, FinFET. ", volume = "7", number = "9", pages = "1153-3", }
