Abstract: This work is the first dowel in a rather wide research
activity in collaboration with Euro Mediterranean Center for Climate
Changes, aimed at introducing scalable approaches in Ocean
Circulation Models. We discuss designing and implementation of
a parallel algorithm for solving the Variational Data Assimilation
(DA) problem on Graphics Processing Units (GPUs). The algorithm
is based on the fully scalable 3DVar DA model, previously proposed
by the authors, which uses a Domain Decomposition approach
(we refer to this model as the DD-DA model). We proceed with
an incremental porting process consisting of 3 distinct stages:
requirements and source code analysis, incremental development of
CUDA kernels, testing and optimization. Experiments confirm the
theoretic performance analysis based on the so-called scale up factor
demonstrating that the DD-DA model can be suitably mapped on
GPU architectures.
Abstract: Current mode circuits like current conveyors are
getting significant attention in current analog ICs design due to their
higher band-width, greater linearity, larger dynamic range, simpler
circuitry, lower power consumption and less chip area. The second
generation current controlled conveyor (CCCII) has the advantage of
electronic adjustability over the CCII i.e. in CCCII; adjustment of the
X-terminal intrinsic resistance via a bias current is possible. The
presented approach is based on the CMOS implementation of second
generation positive (CCCII+), negative (CCCII-) and dual Output
Current Controlled Conveyor (DOCCCII) and its application as
Universal filter. All the circuits have been designed and simulated
using 65nm CMOS technology model parameters on Cadence
Virtuoso / Spectre using 1V supply voltage. Various simulations have
been carried out to verify the linearity between output and input
ports, range of operation frequency, etc. The outcomes show good
agreement between expected and experimental results.