Transceiver for Differential Wave Pipe-Lined Serial Interconnect with Surfing
In the literature, surfing technique has been proposed for single ended wave-pipelined serial interconnects to increase the data transfer rate. In this paper a novel surfing technique is proposed for differential wave-pipelined serial interconnects, which uses a 'Controllable inverter pair' for surfing. To evaluate the efficiency of this technique, a transceiver with transmitter, receiver, delay locked loop (DLL) along with 40mm metal 4 interconnects using the proposed surfing technique is implemented in UMC 180nm technology and their performances are studied through post layout simulations. From the study, it is observed that the proposed scheme permits 1.875 times higher data transmission rate compared to the single ended scheme whose maximum data transfer rate is 1.33 GB/s. The proposed scheme has the ability to receive the correct data even with stuck-at-faults in the complementary line.
[1] International Technology Roadmap for Semiconductors, (2001). Semiconductor Industry Association, 2001, Interconnects section, p. 4.
[2] R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires,” Proc. IEEE, vol. 89, no 4, pp.490-504, April 2001.
[3] H.B. Bakoglu, and J.D. Meindl, "Optimal interconnection circuits for VLSI,” IEEE Trans. Electron Devices ED-32 (5), pp. 903–909, 1985.
[4] C.J. Alpert, A. Devgan, J.P. Fishburn, and S.T. Quay, "Interconnect synthesis without wire tapering, ” IEEE Trans. Computer-Aided Design Integrated Circuits and Systems 20 (1), pp. 90–104, 2001.
[5] H. Zhang, V. George, and J. M. Rabaey, "Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 8, no.3, June 2000.
[6] P. Wang, G. Pei and E. chih-chuan Kan, "Pulsed wave interconnect,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5, May 2004.
[7] P. Jose, G. Patounakis, and K. L. Shepard, "Pulsed current-mode signaling for nearly speed-of- light intra chip communication,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 772-780, April 2006.
[8] J. Nyathi, R.R. Rydberg III and J.G. Delgado-Frias, "Wave-Pipelining the Global Interconnect to Reduce the Associated Delays,” IEEE conference, 2006.
[9] Greenstreet and Ren, "Surfing Interconnect,” In Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’06).
[10] M. Bhaskar, D. Prasankumar and B. Venkataramani, "Design of Differential voltage mode Transmitter for On-chip serial link based on Method of Logical Effort", IEEE International conference ICCCNT, July 2012.
[11] Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann Publishers, Inc., 1998.
[12] P. Murugeswari, G. Anusha, P. Venkateshwarlu, M. Bhaskar, and B. Venkataramani, "A Wide Band Voltage Mode Sense Amplifier Receiver for High Speed Interconnects,” Proceedings of TENCON 2008, IEEE Region 10 conference.
[13] P. Wijetunga and A.F.J. Levi, "3.3 GHz Sense-amplifier in 0.18 µm CMOS technology,” IEEE, ISCAS, pp. 764-765, 2002.
[14] Karutharaja. V, M. Bhaskar and B. Venkataramani, "Synchronization of On-chip Serial Interconnect Transceivers using Delay Locked Loop (DLL),” Proceeding of 2011 IEEE International conference ICSCCN, 2011.
[15] Y Moon, J Choi, K Lee, D-K Jeong, M-K Kim, "An All Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide range Operation and Low-Jitter Performance, ” IEEE Journal of Solid-State Circuits, Vol. 35, No.3, March 2000.
[16] S. Kim, K. Lee, Y. Moon, D. K. Jeong, Y. Choi and H. K. Lim, "A 960-Mb/s/pin Interface for skew tolerant bus using low jitter PLL, ” IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.
[17] Mark G. Johnson, and Edwin L. Hudson, "A Variable Delay Line PLL for CPU-Coprocessor Synchronization,” IEEE Journal of Solid-State Circuits. Vol. 23, No. 5, October, 1988.
[18] H. Ito, J. Inoue, S. Gomi, H.Sugita, K. Okada and K. Masu, "On-chip Transmission line for Long Global Interconnects,” IEEE, IEDM, 2004.
[1] International Technology Roadmap for Semiconductors, (2001). Semiconductor Industry Association, 2001, Interconnects section, p. 4.
[2] R. Ho, K. W. Mai, and M. A. Horowitz, "The future of wires,” Proc. IEEE, vol. 89, no 4, pp.490-504, April 2001.
[3] H.B. Bakoglu, and J.D. Meindl, "Optimal interconnection circuits for VLSI,” IEEE Trans. Electron Devices ED-32 (5), pp. 903–909, 1985.
[4] C.J. Alpert, A. Devgan, J.P. Fishburn, and S.T. Quay, "Interconnect synthesis without wire tapering, ” IEEE Trans. Computer-Aided Design Integrated Circuits and Systems 20 (1), pp. 90–104, 2001.
[5] H. Zhang, V. George, and J. M. Rabaey, "Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 8, no.3, June 2000.
[6] P. Wang, G. Pei and E. chih-chuan Kan, "Pulsed wave interconnect,” IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5, May 2004.
[7] P. Jose, G. Patounakis, and K. L. Shepard, "Pulsed current-mode signaling for nearly speed-of- light intra chip communication,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 772-780, April 2006.
[8] J. Nyathi, R.R. Rydberg III and J.G. Delgado-Frias, "Wave-Pipelining the Global Interconnect to Reduce the Associated Delays,” IEEE conference, 2006.
[9] Greenstreet and Ren, "Surfing Interconnect,” In Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC’06).
[10] M. Bhaskar, D. Prasankumar and B. Venkataramani, "Design of Differential voltage mode Transmitter for On-chip serial link based on Method of Logical Effort", IEEE International conference ICCCNT, July 2012.
[11] Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann Publishers, Inc., 1998.
[12] P. Murugeswari, G. Anusha, P. Venkateshwarlu, M. Bhaskar, and B. Venkataramani, "A Wide Band Voltage Mode Sense Amplifier Receiver for High Speed Interconnects,” Proceedings of TENCON 2008, IEEE Region 10 conference.
[13] P. Wijetunga and A.F.J. Levi, "3.3 GHz Sense-amplifier in 0.18 µm CMOS technology,” IEEE, ISCAS, pp. 764-765, 2002.
[14] Karutharaja. V, M. Bhaskar and B. Venkataramani, "Synchronization of On-chip Serial Interconnect Transceivers using Delay Locked Loop (DLL),” Proceeding of 2011 IEEE International conference ICSCCN, 2011.
[15] Y Moon, J Choi, K Lee, D-K Jeong, M-K Kim, "An All Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide range Operation and Low-Jitter Performance, ” IEEE Journal of Solid-State Circuits, Vol. 35, No.3, March 2000.
[16] S. Kim, K. Lee, Y. Moon, D. K. Jeong, Y. Choi and H. K. Lim, "A 960-Mb/s/pin Interface for skew tolerant bus using low jitter PLL, ” IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.
[17] Mark G. Johnson, and Edwin L. Hudson, "A Variable Delay Line PLL for CPU-Coprocessor Synchronization,” IEEE Journal of Solid-State Circuits. Vol. 23, No. 5, October, 1988.
[18] H. Ito, J. Inoue, S. Gomi, H.Sugita, K. Okada and K. Masu, "On-chip Transmission line for Long Global Interconnects,” IEEE, IEDM, 2004.
@article{"International Journal of Electrical, Electronic and Communication Sciences:66517", author = "Bhaskar M. and Venkataramani B.", title = "Transceiver for Differential Wave Pipe-Lined Serial Interconnect with Surfing", abstract = "In the literature, surfing technique has been proposed for single ended wave-pipelined serial interconnects to increase the data transfer rate. In this paper a novel surfing technique is proposed for differential wave-pipelined serial interconnects, which uses a 'Controllable inverter pair' for surfing. To evaluate the efficiency of this technique, a transceiver with transmitter, receiver, delay locked loop (DLL) along with 40mm metal 4 interconnects using the proposed surfing technique is implemented in UMC 180nm technology and their performances are studied through post layout simulations. From the study, it is observed that the proposed scheme permits 1.875 times higher data transmission rate compared to the single ended scheme whose maximum data transfer rate is 1.33 GB/s. The proposed scheme has the ability to receive the correct data even with stuck-at-faults in the complementary line.
", keywords = "Controllable inverter pair, differential interconnect, serial link, surfing, wave pipelining.", volume = "8", number = "1", pages = "156-8", }
