Modeling of a Second Order Non-Ideal Sigma-Delta Modulator
A behavioral model of a second order switchedcapacitor Sigma-Delta modulator is presented. The purpose of this work is the presentation of a behavioral model of a second order switched capacitor ΣΔ modulator considering (Error due to Clock Jitter, Thermal noise Amplifier Noise, Amplifier Slew-Rate, Non linearity of amplifiers, Gain error, Charge Injection, Clock Feedthrough, and Nonlinear on-resistance). A comparison between the use of MOS switches and the use transmission gate switches use is analyzed.
[1] B. E. Boser and B. A. Wooley, "The design of sigma-delta modulation
analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 22, no.
12, pp. 1298-1308, Dec. 1988.
[2] Schreier R., Temes G. C, "Understanding Delta-Sigma Data
Converters," New York : IEEE Press, 2005.
[3] S. R. Northworthy, R. Schreier, and G. C. Temes, "Delta-Sigma Data
Converters," Piscataway, NJ: IEEE Press, 1997.
[4] G. Temes, "Finite amplifier gain and bandwidth effects in switchedcapacitor
filters," IEEE J. Solid-State Circuits, vol. 15, pp. 358-361,
June 1980.
[5] F. Medeiro et al., "Modeling opamp-induced harmonic distortion for
switched-capacitor SD modulator design," in IEEE Int. Symp. Circuits
Systems, vol. 5, May-Jun. 1994, pp. 445-448.
[6] H. Zare-Hoseini and I. Kale, "On the effects of finite and nonlinear DCgain
on the switched-capacitor delta-sigma modulators," in Proc. IEEE
Int. Symp. Circuits Systems, May 2005, pp. 2547-2550.
[7] S. Lee and K. Yang, "Design a Low-Jitter Clock for High-Speed A/D
Converters". Sensors, vol. 18, no. 10, October 2001.
[8] S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto and
F. Maloberti, "MODELING SIGMA-DELTA MODULATOR NONIDEALITIES
IN SIMULINK®," IEEE International Symposium, pp
384 - 387 vol.2, 1999.
[9] F. MEDEIRO, "CAD Methodology for High-Resolution, High-Speed SD
Modulators with Emphasis in Cascade Multi-Bit Architectures", ICMNeue
Messe, Munich, 2001.
[10] L. Dai, R. Harjani, "CMOS Switched-Op-Amp-Based Sample-and-Hold
Circuit" IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 109-
113, January 2000.
[11] J. Shieh, M. Patil, and A. J. Sheu, "Measurement and analysis of charge
injection in MOS analog switches," IEEE J. Solid-State Circuits, vol.
SSC-22, no. 4, pp. 277-281, Apr. 1987.
[12] J. Shieh, M. Patil, and A. J. Sheu, "Measurement and analysis of charge
injection in MOS analog switches," IEEE J. Solid-State Circuits, vol.
SSC-22, no. 4, pp. 277-281, Apr. 1987.
[13] X. Weize and E. G. Friedman, "Clock-feedthrough in CMOS analog
transmission gate switches," in Annu. IEEE Int. ASIC/SOC Conf., Sep.
2002, pp. 181-185.
[14] Category: Control Systems, File: SD Toolbox (Online). Available:
http://www.mathworks.com/matlabcentral/fileexchange
[15] D.A. Johns, K. Martin, "Analog Integrated Circuit Design, " John Wiley
& Sons, Inc., Toronto, 1997
[16] F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez, J. L. Huertas,
"Modeling OpAmp-Induced Harmonic Distortion for Switched-
Capacitor ΣΔ Modulator Design", Proceedings of ISCAS 94, vol. 5, pp.
445-448, London, UK, 1994.
[1] B. E. Boser and B. A. Wooley, "The design of sigma-delta modulation
analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 22, no.
12, pp. 1298-1308, Dec. 1988.
[2] Schreier R., Temes G. C, "Understanding Delta-Sigma Data
Converters," New York : IEEE Press, 2005.
[3] S. R. Northworthy, R. Schreier, and G. C. Temes, "Delta-Sigma Data
Converters," Piscataway, NJ: IEEE Press, 1997.
[4] G. Temes, "Finite amplifier gain and bandwidth effects in switchedcapacitor
filters," IEEE J. Solid-State Circuits, vol. 15, pp. 358-361,
June 1980.
[5] F. Medeiro et al., "Modeling opamp-induced harmonic distortion for
switched-capacitor SD modulator design," in IEEE Int. Symp. Circuits
Systems, vol. 5, May-Jun. 1994, pp. 445-448.
[6] H. Zare-Hoseini and I. Kale, "On the effects of finite and nonlinear DCgain
on the switched-capacitor delta-sigma modulators," in Proc. IEEE
Int. Symp. Circuits Systems, May 2005, pp. 2547-2550.
[7] S. Lee and K. Yang, "Design a Low-Jitter Clock for High-Speed A/D
Converters". Sensors, vol. 18, no. 10, October 2001.
[8] S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto and
F. Maloberti, "MODELING SIGMA-DELTA MODULATOR NONIDEALITIES
IN SIMULINK®," IEEE International Symposium, pp
384 - 387 vol.2, 1999.
[9] F. MEDEIRO, "CAD Methodology for High-Resolution, High-Speed SD
Modulators with Emphasis in Cascade Multi-Bit Architectures", ICMNeue
Messe, Munich, 2001.
[10] L. Dai, R. Harjani, "CMOS Switched-Op-Amp-Based Sample-and-Hold
Circuit" IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 109-
113, January 2000.
[11] J. Shieh, M. Patil, and A. J. Sheu, "Measurement and analysis of charge
injection in MOS analog switches," IEEE J. Solid-State Circuits, vol.
SSC-22, no. 4, pp. 277-281, Apr. 1987.
[12] J. Shieh, M. Patil, and A. J. Sheu, "Measurement and analysis of charge
injection in MOS analog switches," IEEE J. Solid-State Circuits, vol.
SSC-22, no. 4, pp. 277-281, Apr. 1987.
[13] X. Weize and E. G. Friedman, "Clock-feedthrough in CMOS analog
transmission gate switches," in Annu. IEEE Int. ASIC/SOC Conf., Sep.
2002, pp. 181-185.
[14] Category: Control Systems, File: SD Toolbox (Online). Available:
http://www.mathworks.com/matlabcentral/fileexchange
[15] D.A. Johns, K. Martin, "Analog Integrated Circuit Design, " John Wiley
& Sons, Inc., Toronto, 1997
[16] F. Medeiro, B. Perez-Verdu, A. Rodriguez-Vazquez, J. L. Huertas,
"Modeling OpAmp-Induced Harmonic Distortion for Switched-
Capacitor ΣΔ Modulator Design", Proceedings of ISCAS 94, vol. 5, pp.
445-448, London, UK, 1994.
@article{"International Journal of Electrical, Electronic and Communication Sciences:50461", author = "Abdelghani Dendouga and Nour-Eddine Bouguechal and Souhil Kouda and Samir Barra", title = "Modeling of a Second Order Non-Ideal Sigma-Delta Modulator", abstract = "A behavioral model of a second order switchedcapacitor Sigma-Delta modulator is presented. The purpose of this work is the presentation of a behavioral model of a second order switched capacitor ΣΔ modulator considering (Error due to Clock Jitter, Thermal noise Amplifier Noise, Amplifier Slew-Rate, Non linearity of amplifiers, Gain error, Charge Injection, Clock Feedthrough, and Nonlinear on-resistance). A comparison between the use of MOS switches and the use transmission gate switches use is analyzed.
", keywords = "Charge injection, clock feed through, Sigma Deltamodulators, Sigma Delta non-idealities, switched capacitor.", volume = "4", number = "8", pages = "1109-6", }
