An Approach for Modeling CMOS Gates

A modeling approach for CMOS gates is presented
based on the use of the equivalent inverter. A new model for the
inverter has been developed using a simplified transistor current
model which incorporates the nanoscale effects for the planar
technology. Parametric expressions for the output voltage are
provided as well as the values of the output and supply current to be
compatible with the CCS technology. The model is parametric
according the input signal slew, output load, transistor widths, supply
voltage, temperature and process. The transistor widths of the
equivalent inverter are determined by HSPICE simulations and
parametric expressions are developed for that using a fitting
procedure. Results for the NAND gate shows that the proposed
approach offers sufficient accuracy with an average error in
propagation delay about 5%.

• Spyridon Nikolaidis

• CMOS gate modeling
• Inverter modeling
• transistor current model
• timing model.

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