Abstract: The practical implementation of audio-video coupled speech recognition systems is mainly limited by the hardware complexity to integrate two radically different information capturing devices with good temporal synchronisation. In this paper, we propose a solution based on a smart CMOS image sensor in order to simplify the hardware integration difficulties. By using on-chip image processing, this smart sensor can calculate in real time the X/Y projections of the captured image. This on-chip projection reduces considerably the volume of the output data. This data-volume reduction permits a transmission of the condensed visual information via the same audio channel by using a stereophonic input available on most of the standard computation devices such as PC, PDA and mobile phones. A prototype called VMIKE (Visio-Microphone) has been designed and realised by using standard 0.35um CMOS technology. A preliminary experiment gives encouraged results. Its efficiency will be further investigated in a large variety of applications such as biometrics, speech recognition in noisy environments, and vocal control for military or disabled persons, etc.
Abstract: In this paper, a alternative structure method for
continuous time sigma delta modulator is presented. In this
modulator for implementation of integrators in loop filter second
generation current conveyors are employed. The modulator is
designed in CMOS technology and features low power consumption
(65db),
and with 180khZ bandwidth. Simulation results confirm that this
design is suitable for data converters.
Abstract: Current mode circuits like current conveyors are
getting significant attention in current analog ICs design due to their
higher band-width, greater linearity, larger dynamic range, simpler
circuitry, lower power consumption and less chip area. The second
generation current controlled conveyor (CCCII) has the advantage of
electronic adjustability over the CCII i.e. in CCCII; adjustment of the
X-terminal intrinsic resistance via a bias current is possible. The
presented approach is based on the CMOS implementation of second
generation positive (CCCII+), negative (CCCII-) and dual Output
Current Controlled Conveyor (DOCCCII) and its application as
Universal filter. All the circuits have been designed and simulated
using 65nm CMOS technology model parameters on Cadence
Virtuoso / Spectre using 1V supply voltage. Various simulations have
been carried out to verify the linearity between output and input
ports, range of operation frequency, etc. The outcomes show good
agreement between expected and experimental results.
Abstract: This paper deals with a power-conscious ANDEXOR- Inverter type logic implementation for a complex class of Boolean functions, namely Achilles- heel functions. Different variants of the above function class have been considered viz. positive, negative and pure horn for analysis and simulation purposes. The proposed realization is compared with the decomposed implementation corresponding to an existing standard AND-EXOR logic minimizer; both result in Boolean networks with good testability attribute. It could be noted that an AND-OR-EXOR type logic network does not exist for the positive phase of this unique class of logic function. Experimental results report significant savings in all the power consumption components for designs based on standard cells pertaining to a 130nm UMC CMOS process The simulations have been extended to validate the savings across all three library corners (typical, best and worst case specifications).
Abstract: This paper describes the design of a real-time audiorange
digital oscilloscope and its implementation in 90nm CMOS
FPGA platform. The design consists of sample and hold circuits,
A/D conversion, audio and video processing, on-chip RAM, clock
generation and control logic. The design of internal blocks and
modules in 90nm devices in an FPGA is elaborated. Also the key
features and their implementation algorithms are presented.
Finally, the timing waveforms and simulation results are put
forward.
Abstract: A 10bit, 40 MSps, sample and hold, implemented in 0.18-μm CMOS technology with 3.3V supply, is presented for application in the front-end stage of an analog-to-digital converter. Topology selection, biasing, compensation and common mode feedback are discussed. Cascode technique has been used to increase the dc gain. The proposed opamp provides 149MHz unity-gain bandwidth (wu), 80 degree phase margin and a differential peak to peak output swing more than 2.5v. The circuit has 55db Total Harmonic Distortion (THD), using the improved fully differential two stage operational amplifier of 91.7dB gain. The power dissipation of the designed sample and hold is 4.7mw. The designed system demonstrates relatively suitable response in different process, temperature and supply corners (PVT corners).
Abstract: This paper describes a CMOS four-quadrant
multiplier intended for use in the front-end receiver by utilizing the
square-law characteristic of the MOS transistor in the saturation
region. The circuit is based on 0.35 um CMOS technology simulated
using HSPICE software. The mixer has a third-order inter the power
consumption is 271uW from a single 1.2V power supply. One of the
features of the proposed design is using two MOS transistors
limitation to reduce the supply voltage, which leads to reduce the
power consumption. This technique provides a GHz bandwidth
response and low power consumption.
Abstract: This paper presented a modified efficient inductive
powering link based on ASK modulator and proposed efficient class-
E power amplifier. The design presents the external part which is
located outside the body to transfer power and data to the implanted
devices such as implanted Microsystems to stimulate and monitoring
the nerves and muscles. The system operated with low band
frequency 10MHZ according to industrial- scientific – medical (ISM)
band to avoid the tissue heating. For external part, the modulation
index is 11.1% and the modulation rate 7.2% with data rate 1 Mbit/s
assuming Tbit = 1us. The system has been designed using 0.35-μm
fabricated CMOS technology. The mathematical model is given and
the design is simulated using OrCAD P Spice 16.2 software tool and
for real-time simulation, the electronic workbench MULISIM 11 has
been used.
Abstract: A 1V, 1GHz low noise amplifier (LNA) has been designed and simulated using Spectre simulator in a standard TSMC 0.18um CMOS technology.With low power and noise optimization techniques, the amplifier provides a gain of 24 dB, a noise figure of only 1.2 dB, power dissipation of 14 mW from a 1 V power supply.
Abstract: The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.
Abstract: This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply.
Abstract: A fully on-chip low drop-out (LDO) voltage regulator with 100pF output load capacitor is presented. A novel frequency compensation scheme using current buffer is adopted to realize single dominant pole within the unit gain frequency of the regulation loop, the phase margin (PM) is at least 50 degree under the full range of the load current, and the power supply rejection (PSR) character is improved compared with conventional Miller compensation. Besides, the differentiator provides a high speed path during the load current transient. Implemented in 0.18μm CMOS technology, the LDO voltage regulator provides 100mA load current with a stable 1.8V output voltage consuming 80μA quiescent current.
Abstract: In this paper we present two novel 1-bit full adder
cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output
structures are used to design the adder blocks. Characteristic of
dynamic logic leads to higher speeds than the other standard static
full adder cells. Using HSpice and 0.18┬Ám CMOS technology
exhibits a significant decrease in the cell delay which can result in a
considerable reduction in the power-delay product (PDP). The PDP
of Multi-Output design at 1.8v power supply is around 0.15 femto
joule that is 5% lower than conventional dynamic full adder cell and
at least 21% lower than other static full adders.
Abstract: In this paper, a new BiCMOS CCII and CCCII,
capable of operate at ±0.5V and having wide dynamic range with
achieved bandwidth of 480MHz and 430MHz respectively have been
proposed. The structures have been found to be insensitive to the
threshold voltage variations. The proposed circuits are suitable for
implementation using 0.25μm BiCMOS technology. Pspice
simulations confirm the performance of the proposed structures.
Abstract: This paper introduces an adiabatic register file based
on two-phase CPAL (Complementary Pass-Transistor Adiabatic
Logic circuits) with power-gating scheme, which can operate on a
single-phase power clock. A 32×32 single-phase adiabatic register file
with power-gating scheme has been implemented with TSMC 0.18μm
CMOS technology. All the circuits except for the storage cells employ
two-phase CPAL circuits, and the storage cell is based on the
conventional memory one. The two-phase non-overlap power-clock
generator with power-gating scheme is used to supply the proposed
adiabatic register file. Full-custom layouts are drawn. The energy and
functional simulations have been performed using the net-list
extracted from their layouts. Compared with the traditional static
CMOS register file, HSPICE simulations show that the proposed
adiabatic register file can work very well, and it attains about 73%
energy savings at 100 MHz.
Abstract: The designing of charge pump with high gain Op-
Amp is a challenging task for getting faithful response .Design of
high performance phase locked loop require ,a design of high
performance charge pump .We have designed a operational amplifier
for reducing the error caused by high speed glitch in a transistor and
mismatch currents . A separate Op-Amp has designed in 180 nm
CMOS technology by CADENCE VIRTUOSO tool. This paper
describes the design of high performance charge pump for GHz
CMOS PLL targeting orthogonal frequency division multiplexing
(OFDM) application. A high speed low power consumption Op-Amp
with more than 500 MHz bandwidth has designed for increasing the
speed of charge pump in Phase locked loop.
Abstract: A 2.4GHz (RF) down conversion Gilbert Cell mixer,
implemented in a 0.18-μm CMOS technology with a 1.8V supply, is
presented. Current bleeding (charge injection) technique has been
used to increase the conversion gain and the linearity of the mixer.
The proposed mixer provides 10.75 dB conversion gain ( C G ) with
14.3mw total power consumption. The IIP3 and 1-dB compression
point of the mixer are 8dbm and -4.6dbm respectively, at 300 MHz
IF frequencies. Comparing the current design against the
conventional mixer design, demonstrates better performance in the
conversion gain, linearity, noise figure and port-to-port isolation.
Abstract: Adjacent Hall microsensors, comprising a silicon
substrate and four contacts, providing simultaneously two supply inputs and two differential outputs, are characterized. The voltage
related sensitivity is in the order of 0.11T-1, and a cancellation method for offset compensation is used, achieving residual offset in
the micro scale which is also compared to a single Hall plate.
Abstract: This paper proposes a low power SRAM based on
five transistor SRAM cell. Proposed SRAM uses novel word-line
decoding such that, during read/write operation, only selected cell
connected to bit-line whereas, in conventional SRAM (CV-SRAM),
all cells in selected row connected to their bit-lines, which in turn
develops differential voltages across all bit-lines, and this makes
energy consumption on unselected bit-lines. In proposed SRAM
memory array divided into two halves and this causes data-line
capacitance to reduce. Also proposed SRAM uses one bit-line and
thus has lower bit-line leakage compared to CV-SRAM.
Furthermore, the proposed SRAM incurs no area overhead, and has
comparable read/write performance versus the CV-SRAM.
Simulation results in standard 0.25μm CMOS technology shows in
worst case proposed SRAM has 80% smaller dynamic energy
consumption in each cycle compared to CV-SRAM. Besides, energy
consumption in each cycle of proposed SRAM and CV-SRAM
investigated analytically, the results of which are in good agreement
with the simulation results.
Abstract: In this paper, a modified CCCII is presented. We have used a current mirror with low supply voltage. This circuit is operated at low supply voltage of ±1V. Tspice simulations for TSMC 0.18μm CMOS Technology has shown that the current and voltage bandwidth are respectively 3.34GHz and 4.37GHz, and parasitic resistance at port X has a value of 169.320 for a control current of 120μA. In order to realize this circuit, we have implemented in this first step a universal current mode filter where the frequency can reach the 134.58MHz. In the second step, we have implemented two simulated inductors: one floating and the other grounded. These two inductors are operated in high frequency and variable depending on bias current I0. Finally, we have used the two last inductors respectively to implement two sinusoidal oscillators domains of frequencies respectively: [470MHz, 692MHz], and [358MHz, 572MHz] for bias currents I0 [80μA, 350μA].