Abstract: This paper presents the design and layout of a two stage, high speed operational amplifiers using standard 0.35um CMOS technology. The design procedure involves designing the bias circuit, the differential input pair, and the gain stage using CAD tools. Both schematic and layout of the operational amplifier along with the comparison in the results of the two has been presented. The operational amplifier designed, has a gain of 93.51db at low frequencies. It has a gain bandwidth product of 55.07MHz, phase margin of 51.9º and a slew rate of 22v/us for a load of capacitor of 10pF.
Abstract: To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.
Abstract: This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on Instrumentation amplifier and it is useful for reducing offset In Wheatstone Bridge. The obtained gain is 645 with 1μv/°c Equivalent drift and 1.58mw power consumption. A Schmitt trigger and multiplexer circuit control output node. a high speed counter is designed in this work .the proposed circuit is designed and simulated In 0.18μm CMOS technology with 1.8v power supply.
Abstract: Photo-BJMOSFET (Bipolar Junction Metal-Oxide-
Semiconductor Field Effect Transistor) fabricated on SOI film was proposed. ITO film is adopted in the device as gate electrode to reduce
light absorption. Depletion region but not inversion region is formed
in film by applying gate voltage (but low reverse voltage) to achieve
high photo-to-dark-current ratio. Comparisons of photoelectriccharacteristics
executed among VGK=0V, 0.3V, 0.6V, 0.9V and 1.0V
(reverse voltage VAK is equal to 1.0V for total area of 10×10μm2). The
results indicate that the greatest improvement in photo-to-dark-current
ratio is achieved up to 2.38 at VGK=0.6V. In addition,
photo-BJMOSFET is compatible with CMOS integration due to big
input resistance
Abstract: A fast settling multipath CMOS OTA for high speed
switched capacitor applications is presented here. With the basic
topology similar to folded-cascode, bandwidth and DC gain of the
OTA are enhanced by adding extra paths for signal from input to
output. Designed circuit is simulated with HSPICE using level 49
parameters (BSIM 3v3) in 0.35mm standard CMOS technology. DC
gain achieved is 56.7dB and Unity Gain Bandwidth (UGB) obtained
is 1.15GHz. These results confirm that adding extra paths for signal
can improve DC gain and UGB of folded-cascode significantly.
Abstract: A high precision temperature insensitive current and voltage reference generator is presented. It is specifically developed for temperature compensated oscillator. The circuit, designed using MXIC 0.5um CMOS technology, has an operating voltage that ranges from 2.6V to 5V and generates a voltage of 1.21V and a current of 6.38 ӴA. It exhibits a variation of ±0.3nA for the current reference and a stable output for voltage reference as the temperature is varied from 0°C to 70°C. The power supply rejection ratio obtained without any filtering capacitor at 100Hz and 10MHz is -30dB and -12dB respectively.
Abstract: In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple current mirror with input and output voltage requirements less than that of a simple current mirror is presented. These features are achieved with very simple structure avoiding extra large node impedances to ensure high bandwidth operation. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Such outstanding features of this current mirror as high output impedance ~384K, low input impedance~6.4, wide bandwidth~178MHz, low input voltage ~ 362mV, low output voltage ~ 38mV and low current transfer error ~4% (all at 50μA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35μm CMOS technology with HSPICE are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror.
Abstract: As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.
Abstract: This paper presents a low-voltage low-power differential linear transconductor with near rail-to-rail input swing. Based on the current-mirror OTA topology, the proposed transconductor combines the Flipped Voltage Follower (FVF) technique to linearize the transconductor behavior that leads to class- AB linear operation and the virtual transistor technique to lower the effective threshold voltages of the transistors which offers an advantage in terms of low supply requirement. Design of the OTA has been discussed. It operates at supply voltages of about ±0.8V. Simulation results for 0.18μm TSMC CMOS technology show a good input range of 1Vpp with a high DC gain of 81.53dB and a total harmonic distortion of -40dB at 1MHz for an input of 1Vpp. The main aim of this paper is to present and compare new OTA design with high transconductance, which has a potential to be used in low voltage applications.
Abstract: An on chip low drop out voltage regulator that
employs elegant compensation scheme is presented in this paper. The
novelty in this design is that the device parasitic capacitances are
exploited for compensation at different loads. The proposed LDO is
designed to provide a constant voltage of 1.2V and is implemented in
UMC 180 nano meter CMOS technology. The voltage regulator
presented improves stability even at lighter loads and enhances line
and load regulation.
Abstract: A new interface circuit for capacitive sensor is
presented. This paper presents the design and simulation of soil
moisture capacitive sensor interface circuit based on phase
differential technique. The circuit has been designed and fabricated
using MIMOS- 0.35"m CMOS technology. Simulation and test
results show linear characteristic from 36 – 52 degree phase
difference, representing 0 – 100% in soil moisture level. Test result
shows the circuit has sensitivity of 0.79mV/0.10 phase difference,
translating into resolution of 10% soil moisture level.
Abstract: Multiplication algorithms have considerable effect on
processors performance. A new high-speed, low-power
multiplication algorithm has been presented using modified Dadda
tree structure. Three important modifications have been implemented
in inner product generation step, inner product reduction step and
final addition step. Optimized algorithms have to be used into basic
computation components, such as multiplication algorithms. In this
paper, we proposed a new algorithm to reduce power, delay, and
transistor count of a multiplication algorithm implemented using low
power modified counter. This work presents a novel design for
Dadda multiplication algorithms. The proposed multiplication
algorithm includes structured parts, which have important effect on
inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid
adder is presented for fast, low voltage applications. The new 64-bit
adder uses a new circuit to implement the proposed carry hybrid
adder. The new adder using 80 nm CMOS technology has been
implemented on 700 MHz clock frequency. The proposed
multiplication algorithm has achieved 14 percent improvement in
transistor count, 13 percent reduction in delay and 12 percent
modification in power consumption in compared with conventional
designs.
Abstract: A new low-voltage floating gate MOSFET (FGMOS)
based squarer using square law characteristic of the FGMOS is
proposed in this paper. The major advantages of the squarer are simplicity,
rail-to-rail input dynamic range, low total harmonic distortion,
and low power consumption. The proposed circuit is biased without
body effect. The circuit is designed and simulated using SPICE in
0.25μm CMOS technology. The squarer is operated at the supply
voltages of ±0.75V . The total harmonic distortion (THD) for the
input signal 0.75Vpp at 25 KHz, and maximum power consumption
were found to be less than 1% and 319μW respectively.
Abstract: This paper presents a novel CMOS four-transistor
SRAM cell for very high density and low power embedded SRAM
applications as well as for stand-alone SRAM applications. This cell
retains its data with leakage current and positive feedback without
refresh cycle. The new cell size is 20% smaller than a conventional
six-transistor cell using same design rules. Also proposed cell uses
two word-lines and one pair bit-line. Read operation perform from
one side of cell, and write operation perform from another side of
cell, and swing voltage reduced on word-lines thus dynamic power
during read/write operation reduced. The fabrication process is fully
compatible with high-performance CMOS logic technologies,
because there is no need to integrate a poly-Si resistor or a TFT load.
HSPICE simulation in standard 0.25μm CMOS technology confirms
all results obtained from this paper.
Abstract: This paper describes the design of a programmable
FSK-modulator based on VCO and its implementation in 0.35m
CMOS process. The circuit is used to transmit digital data at
100Kbps rate in the frequency range of 400-600MHz. The design
and operation of the modulator is discussed briefly. Further the
characteristics of PLL, frequency synthesizer, VCO and the whole
design are elaborated. The variation among the proposed and tested
specifications is presented. Finally, the layout of sub-modules, pin
configurations, final chip and test results are presented.
Abstract: A active inductor in CMOS techonology with a supply voltage of 1.8V is presented. The value of the inductance L can be in the range from 0.12nH to 0.25nH in high frequency(HF). The proposed active inductor is designed in TSMC 0.18-um CMOS technology. The power dissipation of this inductor can retain constant at all operating frequency bands and consume around 20mW from 1.8V power supply. Inductors designed by integrated circuit occupy much smaller area, for this reason,attracted researchers attention for more than decade. In this design we used Advanced Designed System (ADS) for simulating cicuit.
Abstract: RF performance of SOI CMOS device has attracted
significant amount of interest recently. In order to improve RF
parameters, Strained Si/Relaxed Si0.8Ge0.2 investigated as a
replacement for Si technology .Enhancement of carrier mobility
associated with strain engineering makes Strained Si a promising
candidate for improving RF performance of CMOS technology.
From the simulation, the cut-off frequency is estimated to be 224
GHZ, whereas in SOI at similar bias is about 188 GHZ. Therefore,
Strained Si exhibits 19% improvement in cut-off frequency over
similar Si counterpart. In this paper, Ion/Ioff ratio is studied as one of
the key parameters in logic and digital application. Strained Si/SiGe
demonstrates better Ion/Ioff characteristic than SOI, in similar channel
length of 100 nm.Another important key analog figures of merit such
as Early Voltage (VEA) ,transconductance vs drain current (gm /Ids)
are studied. They introduce the efficiency of the devices to convert
dc power into ac frequency.
Abstract: This paper presents a new true RMS-to-DC converter
circuit based on a square-root-domain squarer/divider. The circuit is
designed by employing up-down translinear loop and using of
MOSFET transistors that operate in strong inversion saturation
region. The converter offer advantages of two-quadrant input current,
low circuit complexity, low supply voltage (1.2V) and immunity
from the body effect. The circuit has been simulated by HSPICE.
The simulation results are seen to conform to the theoretical analysis
and shows benefits of the proposed circuit.
Abstract: Nowadays it is a trend for electronic circuit designers to
integrate all system components on a single-chip. This paper proposed
the design of a single-chip proportional to absolute temperature
(PTAT) sensor including a voltage reference circuit using CEDEC
0.18m CMOS Technology. It is a challenge to design asingle-chip
wide range linear response temperature sensor for many applications.
The channel widths between the compensation transistor and the
reference transistor are critical to design the PTAT temperature sensor
circuit. The designed temperature sensor shows excellent linearity
between -100°C to 200° and the sensitivity is about 0.05mV/°C.
The chip is designed to operate with a single voltage source of 1.6V.