Abstract: Current mode circuits like current conveyors are
getting significant attention in current analog ICs design due to their
higher band-width, greater linearity, larger dynamic range, simpler
circuitry, lower power consumption and less chip area. The second
generation current controlled conveyor (CCCII) has the advantage of
electronic adjustability over the CCII i.e. in CCCII; adjustment of the
X-terminal intrinsic resistance via a bias current is possible. The
presented approach is based on the CMOS implementation of second
generation positive (CCCII+), negative (CCCII-) and dual Output
Current Controlled Conveyor (DOCCCII) and its application as
Universal filter. All the circuits have been designed and simulated
using 65nm CMOS technology model parameters on Cadence
Virtuoso / Spectre using 1V supply voltage. Various simulations have
been carried out to verify the linearity between output and input
ports, range of operation frequency, etc. The outcomes show good
agreement between expected and experimental results.
Abstract: In this paper, a modified CCCII is presented. We have used a current mirror with low supply voltage. This circuit is operated at low supply voltage of ±1V. Tspice simulations for TSMC 0.18μm CMOS Technology has shown that the current and voltage bandwidth are respectively 3.34GHz and 4.37GHz, and parasitic resistance at port X has a value of 169.320 for a control current of 120μA. In order to realize this circuit, we have implemented in this first step a universal current mode filter where the frequency can reach the 134.58MHz. In the second step, we have implemented two simulated inductors: one floating and the other grounded. These two inductors are operated in high frequency and variable depending on bias current I0. Finally, we have used the two last inductors respectively to implement two sinusoidal oscillators domains of frequencies respectively: [470MHz, 692MHz], and [358MHz, 572MHz] for bias currents I0 [80μA, 350μA].