Growth of Non-Polar a-Plane AlGaN Epilayer with High Crystalline Quality and Smooth Surface Morphology

Non-polar a-plane AlGaN epilayers of high structural quality have been grown on r-sapphire substrate by using metalorganic chemical vapor deposition (MOCVD). A graded non-polar AlGaN buffer layer with variable aluminium concentration was used to improve the structural quality of the non-polar a-plane AlGaN epilayer. The characterisations were carried out by high-resolution X-ray diffraction (HR-XRD), atomic force microscopy (AFM) and Hall effect measurement. The XRD and AFM results demonstrate that the Al-composition-graded non-polar AlGaN buffer layer significantly improved the crystalline quality and the surface morphology of the top layer. A low root mean square roughness 1.52 nm is obtained from AFM, and relatively low background carrier concentration down to 3.9×  cm-3 is obtained from Hall effect measurement.

Fabrication of High-Power AlGaN/GaN Schottky Barrier Diode with Field Plate Design

In this letter, we demonstrate high-performance AlGaN/GaN planar Schottky barrier diodes (SBDs) on the silicon substrate with field plate structure for increasing breakdown voltage VB. A low turn-on resistance RON (3.55 mΩ-cm2), low reverse leakage current (< 0.1 µA) at -100 V, and high reverse breakdown voltage VB (> 1.1 kV) SBD has been fabricated. A virgin SBD exhibited a breakdown voltage (measured at 1 mA/mm) of 615 V, and with the field plate technology device exhibited a breakdown voltage (measured at 1 mA/mm) of 1525 V (the anode–cathode distance was LAC = 40 µm). Devices without the field plate design exhibit a Baliga’s figure of merit of VB2/ RON = 60.2 MW/cm2, whereas devices with the field plate design show a Baliga’s figure of merit of VB2/ RON = 340.9 MW/cm2 (the anode–cathode distance was LAC = 20 µm).

Capacitance Models of AlGaN/GaN High Electron Mobility Transistors

In this study, we report calculations of gate capacitance of AlGaN/GaN HEMTs with nextnano device simulation software. We have used a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. These simulations explore various device structures with different values of barrier thickness and channel thickness. A detailed understanding of the impact of gate capacitance in HEMTs will allow us to determine their role in future 10 nm physical gate length node.

Control of an Asymmetrical Design of a Pneumatically Actuated Ambidextrous Robot Hand

The Ambidextrous Robot Hand is a robotic device with the purpose to mimic either the gestures of a right or a left hand. The symmetrical behavior of its fingers allows them to bend in one way or another keeping a compliant and anthropomorphic shape. However, in addition to gestures they can reproduce on both sides, an asymmetrical mechanical design with a three tendons routing has been engineered to reduce the number of actuators. As a consequence, control algorithms must be adapted to drive efficiently the ambidextrous fingers from one position to another and to include grasping features. These movements are controlled by pneumatic muscles, which are nonlinear actuators. As their elasticity constantly varies when they are under actuation, the length of pneumatic muscles and the force they provide may differ for a same value of pressurized air. The control algorithms introduced in this paper take both the fingers asymmetrical design and the pneumatic muscles nonlinearity into account to permit an accurate control of the Ambidextrous Robot Hand. The finger motion is achieved by combining a classic PID controller with a phase plane switching control that turns the gain constants into dynamic values. The grasping ability is made possible because of a sliding mode control that makes the fingers adapt to the shape of an object before strengthening their positions.

Static and Dynamic Characteristics of an Appropriated and Recessed n-GaN/AlGaN/GaN HEMT

The objective of this paper is to simulate static I-V and dynamic characteristics of an appropriated and recessed n-GaN/AlxGa1-xN/GaN high electron mobility (HEMT). Using SILVACO TCAD device simulation, and optimized technological parameters; we calculate the drain-source current (lDS) as a function of the drain-source voltage (VDS) for different values ​​of the gate-source voltage (VGS), and the drain-source current (lDS) depending on the gate-source voltage (VGS) for a drain-source voltage (VDS) of 20 V, for various temperatures. Then, we calculate the cut-off frequency and the maximum oscillation frequency for different temperatures. We obtain a high drain-current equal to 60 mA, a low knee voltage (Vknee) of 2 V, a high pinch-off voltage (VGS0) of 53.5 V, a transconductance greater than 600 mS/mm, a cut-off frequency (fT) of about 330 GHz, and a maximum oscillation frequency (fmax) of about 1 THz.

Analysis of Genotype Size for an Evolvable Hardware System

The evolution of logic circuits, which falls under the heading of evolvable hardware, is carried out by evolutionary algorithms. These algorithms are able to automatically configure reconfigurable devices. One of main difficulties in developing evolvable hardware with the ability to design functional electrical circuits is to choose the most favourable EA features such as fitness function, chromosome representations, population size, genetic operators and individual selection. Until now several researchers from the evolvable hardware community have used and tuned these parameters and various rules on how to select the value of a particular parameter have been proposed. However, to date, no one has presented a study regarding the size of the chromosome representation (circuit layout) to be used as a platform for the evolution in order to increase the evolvability, reduce the number of generations and optimize the digital logic circuits through reducing the number of logic gates. In this paper this topic has been thoroughly investigated and the optimal parameters for these EA features have been proposed. The evolution of logic circuits has been carried out by an extrinsic evolvable hardware system which uses (1+λ) evolution strategy as the core of the evolution.

InAlGaN Quaternary Multi-Quantum Wells UVLaser Diode Performance and Characterization

The InAlGaN alloy has only recently began receiving serious attention into its growth and application. High quality InGaN films have led to the development of light emitting diodes (LEDs) and blue laser diodes (LDs). The quaternary InAlGaN however, represents a more versatile material since the bandgap and lattice constant can be independently varied. We report an ultraviolet (UV) quaternary InAlGaN multi-quantum wells (MQWs) LD study by using the simulation program of Integrated System Engineering (ISE TCAD). Advanced physical models of semiconductor properties were used in order to obtain an optimized structure. The device performance which is affected by piezoelectric and thermal effects was studied via drift-diffusion model for carrier transport, optical gain and loss. The optical performance of the UV LD with different numbers of quantum wells was numerically investigated. The main peak of the emission wavelength for double quantum wells (DQWs) was shifted from 358 to 355.8 nm when the forward current was increased. Preliminary simulated results indicated that better output performance and lower threshold current could be obtained when the quantum number is four, with output power of 130 mW and threshold current of 140 mA.

Chose the Right Mutation Rate for Better Evolve Combinational Logic Circuits

Evolvable hardware (EHW) is a developing field that applies evolutionary algorithm (EA) to automatically design circuits, antennas, robot controllers etc. A lot of research has been done in this area and several different EAs have been introduced to tackle numerous problems, as scalability, evolvability etc. However every time a specific EA is chosen for solving a particular task, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade the selection of the right parameters for the EA-s components for solving different “test-problems" has been investigated. In this paper the behaviour of mutation rate for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies the number of inputs of each logic gates, the functionality (for example from AND to NOR) and the connectivity between logic gates. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates for the evolved circuits. The experimental results found provide the behaviour of the mutation rate during evolution for the design and optimization of simple logic circuits. The experimental results propose the best mutation rate to be used for designing combinational logic circuits. The research presented is particular important for those who would like to implement a dynamic mutation rate inside the evolutionary algorithm for evolving digital circuits. The researches on the mutation rate during the last 40 years are also summarized.

FPGA-based Systems for Evolvable Hardware

Since 1992, year where Hugo de Garis has published the first paper on Evolvable Hardware (EHW), a period of intense creativity has followed. It has been actively researched, developed and applied to various problems. Different approaches have been proposed that created three main classifications: extrinsic, mixtrinsic and intrinsic EHW. Each of these solutions has a real interest. Nevertheless, although the extrinsic evolution generates some excellent results, the intrinsic systems are not so advanced. This paper suggests 3 possible solutions to implement the run-time configuration intrinsic EHW system: FPGA-based Run-Time Configuration system, JBits-based Run-Time Configuration system and Multi-board functional-level Run-Time Configuration system. The main characteristic of the proposed architectures is that they are implemented on Field Programmable Gate Array. A comparison of proposed solutions demonstrates that multi-board functional-level run-time configuration is superior in terms of scalability, flexibility and the implementation easiness.

Feasibility of the Evolutionary Algorithm using Different Behaviours of the Mutation Rate to Design Simple Digital Logic Circuits

The evolutionary design of electronic circuits, or evolvable hardware, is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under the control of evolutionary algorithms. Several researchers have used evolvable hardware to design electrical circuits. Every time that one particular algorithm is selected to carry out the evolution, it is necessary that all its parameters, such as mutation rate, population size, selection mechanisms etc. are tuned in order to achieve the best results during the evolution process. This paper investigates the abilities of evolution strategy to evolve digital logic circuits based on programmable logic array structures when different mutation rates are used. Several mutation rates (fixed and variable) are analyzed and compared with each other to outline the most appropriate choice to be used during the evolution of combinational logic circuits. The experimental results outlined in this paper are important as they could be used by every researcher who might need to use the evolutionary algorithm to design digital logic circuits.

EHW from Consumer Point of View: Consumer-Triggered Evolution

Evolvable Hardware (EHW) has been regarded as adaptive system acquired by wide application market. Consumer market of any good requires diversity to satisfy consumers- preferences. Adaptation of EHW is a key technology that could provide individual approach to every particular user. This situation raises a question: how to set target for evolutionary algorithm? The existing techniques do not allow consumer to influence evolutionary process. Only designer at the moment is capable to influence the evolution. The proposed consumer-triggered evolution overcomes this problem by introducing new features to EHW that help adaptive system to obtain targets during consumer stage. Classification of EHW is given according to responsiveness, imitation of human behavior and target circuit response. Home intelligent water heating system is considered as an example.

Performance of InGaN/GaN Laser Diode Based on Quaternary Alloys Stopper and Superlattice Layers

The optical properties of InGaN/GaN laser diode based on quaternary alloys stopper and superlattice layers are numerically studied using ISE TCAD (Integrated System Engineering) simulation program. Improvements in laser optical performance have been achieved using quaternary alloy as superlattice layers in InGaN/GaN laser diodes. Lower threshold current of 18 mA and higher output power and slope efficiency of 22 mW and 1.6 W/A, respectively, at room temperature have been obtained. The laser structure with InAlGaN quaternary alloys as an electron blocking layer was found to provide better laser performance compared with the ternary AlxGa1-xN blocking layer.

Mutation Rate for Evolvable Hardware

Evolvable hardware (EHW) refers to a selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). A lot of research has been done in this area several different EA have been introduced. Every time a specific EA is chosen for solving a particular problem, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade a lot of research has been carried out in order to identify the best parameters for the EA-s components for different “test-problems". However different researchers propose different solutions. In this paper the behaviour of mutation rate on (1+λ) evolution strategy (ES) for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies values of the logic cell inputs, the cell type (for example from AND to NOR) and the circuit output. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates used for the evolved circuits. The experimental results found provide the behaviour of the mutation rate to be used during evolution for the design and optimization of logic circuits. The researches on the best mutation rate during the last 40 years are also summarized.

Raman Scattering and PL Studies on AlGaN/GaN HEMT Layers on 200 mm Si(111)

The crystalline quality of the AlGaN/GaN high electron mobility transistor (HEMT) structure grown on a 200 mm silicon substrate has been investigated using UV-visible micro- Raman scattering and photoluminescence (PL). The visible Raman scattering probes the whole nitride stack with the Si substrate and shows the presence of a small component of residual in-plane stress in the thick GaN buffer resulting from a wafer bowing, while the UV micro-Raman indicates a tensile interfacial stress induced at the top GaN/AlGaN/AlN layers. PL shows a good crystal quality GaN channel where the yellow band intensity is very low compared to that of the near-band-edge transition. The uniformity of this sample is shown by measurements from several points across the epiwafer.

On the Operation Mechanism and Device Modeling of AlGaN/GaN High Electron Mobility Transistors (HEMTs)

In this work, the physical based device model of AlGaN/GaN high electron mobility transistors (HEMTs) has been established and the corresponding device operation behavior has been investigated also by using Sentaurus TCAD from Synopsys. Advanced AlGaN/GaN hetero-structures with GaN cap layer and AlN spacer have been considered and the GaN cap layer and AlN spacer are found taking important roles on the gate leakage blocking and off-state breakdown voltage enhancement.

Surface Phonon Polariton in InAlGaN Quaternary Alloys

III-nitride quaternary InxAlyGa1-x-yN alloys have experienced considerable interest as potential materials for optoelectronic applications. Despite these interesting applications and the extensive efforts to understand their fundamental properties, research on its fundamental surface property, i.e., surface phonon polariton (SPP) has not yet been reported. In fact, the SPP properties have been shown to provide application for some photonic devices. Hence, there is an absolute need for thorough studies on the SPP properties of this material. In this work, theoretical study on the SPP modes in InAlGaN quaternary alloys are reported. Attention is focus on the wurtzite (α-) structure InxAlyGa1-x-yN semi-crystal with different In composition, x ranging from 0 to 0.10 and constant Al composition, y = 0.06. The SPP modes are obtained through the theoretical simulation by means of anisotropy model. The characteristics of SP dispersion curves are discussed. Accessible results in terms of the experimental point of view are also given. Finally, the results revealed that the SPP mode of α-InxAlyGa1-x-yN semiconductors exhibits two-mode behavior.

Grid Based and Random Based Ant Colony Algorithms for Automatic Hose Routing in 3D Space

Ant Colony Algorithms have been applied to difficult combinatorial optimization problems such as the travelling salesman problem and the quadratic assignment problem. In this paper gridbased and random-based ant colony algorithms are proposed for automatic 3D hose routing and their pros and cons are discussed. The algorithm uses the tessellated format for the obstacles and the generated hoses in order to detect collisions. The representation of obstacles and hoses in the tessellated format greatly helps the algorithm towards handling free-form objects and speeds up computation. The performance of algorithm has been tested on a number of 3D models.

Multi-board Run-time Reconfigurable Implementation of Intrinsic Evolvable Hardware

A multi-board run-time reconfigurable (MRTR) system for evolvable hardware (EHW) is introduced with the aim to implement on hardware the bidirectional incremental evolution (BIE) method. The main features of this digital intrinsic EHW solution rely on the multi-board approach, the variable chromosome length management and the partial configuration of the reconfigurable circuit. These three features provide a high scalability to the solution. The design has been written in VHDL with the concern of not being platform dependant in order to keep a flexibility factor as high as possible. This solution helps tackling the problem of evolving complex task on digital configurable support.

The Role of Ga to Improve AlN-Nucleation Layer for Al0.1Ga0.9N/Si(111)

Group-III nitride material as particularly AlxGa1-xN is one of promising optoelectronic materials to require for shortwavelength devices. To achieve the high-quality AlxGa1-xN films for a high performance of such devices, AlN-nucleation layers are the important factor. To improve the AlN-nucleation layers with a variation of Ga-addition, XRD measurements were conducted to analyze the crystalline quality of the subsequent Al0.1Ga0.9N with the minimum ω-FWHMs of (0002) and (10-10) reflections of 425 arcsec and 750 arcsec, respectively. SEM and AFM measurements were performed to observe the surface morphology and TEM measurements to identify the microstructures and orientations. Results showed that the optimized Ga-atoms in the Al(Ga)Nnucleation layers improved the surface diffusion to form moreuniform crystallites in structure and size, better alignment of each crystallite, and better homogeneity of island distribution. This, hence, improves the orientation of epilayers on the Si-surface and finally improves the crystalline quality and reduces the residual strain of subsequent Al0.1Ga0.9N layers.