Abstract: To study the influence of different organic amendments on the quality of poultry manure compost, three pilot composting trials were carried out with different mixes: poultry manure/carcasse meal/ashes/grape pomace (Pile 1), poultry manure/ cellulosic sludge (Pile 2) and poultry manure (Pile 3). For all piles, wood chips were applied as bulking agent. The process was monitored, over time, by evaluating standard physical and chemical parameters, such as, pH, electric conductivity, moisture, organic matter and ash content, total carbon and total nitrogen content, carbon/nitrogen ratio (C/N) and content in mineral elements. Piles 1 and 2 reached a thermophilic phase, however having different trends. Pile 1 reached this phase earlier than Pile 2. For both, the pH showed a slight alkaline character and the electric conductivity was lower than 2 mS/cm. Also, the initial C/N value was 22 and reached values lower than 15 at the end of composting process. The total N content of the Pile 1 increased slightly during composting, in contrast with the others piles. At the end of composting process, the phosphorus content ranged between 54 and 236 mg/kg dry matter, for Pile 2 and 3, respectively. Generally, the Piles 1 and 3 exhibited similar heavy metals content. This study showed that organic amendments can be used as carbon source, given that the final composts presented parameters within the range of those recommended in the 2nd Draft of EU regulation proposal (DG Env.A.2 2001) for compost quality.
Abstract: For briquetting of metal chips are used hydraulic and
mechanical presses. The density of the briquettes in this case is about
60% - 70 % on the density of solid metal. In this work are presented
the results of experimental studies for briquetting of metal chips, by
using a new technology for impact briquetting. The used chips are by
Armco iron, steel, cast iron, copper, aluminum and brass. It has been
found that: (i) in a controlled impact the density of the briquettes can
be increases up to 30%; (ii) at the same specific impact energy Es
(J/sm3) the density of the briquettes increases with increasing of the
impact velocity; (iii), realization of the repeated impact leads to
decrease of chips density, which can be explained by distribution of
elastic waves in the briquette.
Abstract: While the feature sizes of recent Complementary Metal
Oxid Semiconductor (CMOS) devices decrease the influence of static
power prevails their energy consumption. Thus, power savings that
benefit from Dynamic Frequency and Voltage Scaling (DVFS) are
diminishing and temporal shutdown of cores or other microchip
components become more worthwhile. A consequence of powering off unused parts of a chip is that the
relative difference between idle and fully loaded power consumption
is increased. That means, future chips and whole server systems gain
more power saving potential through power-aware load balancing,
whereas in former times this power saving approach had only
limited effect, and thus, was not widely adopted. While powering
off complete servers was used to save energy, it will be superfluous
in many cases when cores can be powered down. An important
advantage that comes with that is a largely reduced time to respond
to increased computational demand. We include the above developments in a server power model
and quantify the advantage. Our conclusion is that strategies from
datacenters when to power off server systems might be used in the
future on core level, while load balancing mechanisms previously
used at core level might be used in the future at server level.
Abstract: This paper will discuss how we optimize our physical
verification flow in our IC Design Department having various rule
decks from multiple foundries. Our ultimate goal is to achieve faster
time to tape-out and avoid schedule delay. Currently the physical
verification runtimes and memory usage have drastically increased
with the increasing number of design rules, design complexity, and
the size of the chips to be verified. To manage design violations, we
use a number of solutions to reduce the amount of violations needed
to be checked by physical verification engineers. The most important
functions in physical verifications are DRC (design rule check), LVS
(layout vs. schematic), and XRC (extraction). Since we have a
multiple number of foundries for our design tape-outs, we need a
flow that improve the overall turnaround time and ease of use of the
physical verification process. The demand for fast turnaround time is
even more critical since the physical design is the last stage before
sending the layout to the foundries.
Abstract: A multilayer passive shield composed of low-activity
lead (Pb), copper (Cu), tin (Sn) and iron (Fe) was designed and
manufactured for a coaxial HPGe detector placed at a surface
laboratory for reducing background radiation and radiation dose to
the personnel. The performance of the shield was evaluated and
efficiency curves of the detector were plotted by using of various
standard sources in different distances. Monte Carlo simulations and
a set of TLD chips were used for dose estimation in two distances of
20 and 40 cm. The results show that the shield reduced background
spectrum and the personnel dose more than 95%.
Abstract: In this paper, relationship between different properties
of IC concrete and water cement ratio, obtained from a
comprehensive experiment conducted on IC using local materials
(Burnt clay chips- BC) is presented. In addition, saturated SAP was
used as an IC material in some cases. Relationships have been
developed through regression analysis. The focus of this analysis is
on developing relationship between a dependent variable and an
independent variable. Different percent replacements of BC and
water cement ratios were used. Compressive strength, modulus of
elasticity, water permeability and chloride permeability were tested
and variations of these parameters were analyzed with respect to
water cement ratio.
Abstract: Floorplanning plays a vital role in the physical design
process of Very Large Scale Integrated (VLSI) chips. It is an
essential design step to estimate the chip area prior to the optimized
placement of digital blocks and their interconnections. Since VLSI
floorplanning is an NP-hard problem, many optimization techniques
were adopted in the literature. In this work, a music-inspired
Harmony Search (HS) algorithm is used for the fixed die outline
constrained floorplanning, with the aim of reducing the total chip
area. HS draws inspiration from the musical improvisation process of
searching for a perfect state of harmony. Initially, B*-tree is used to
generate the primary floorplan for the given rectangular hard
modules and then HS algorithm is applied to obtain an optimal
solution for the efficient floorplan. The experimental results of the
HS algorithm are obtained for the MCNC benchmark circuits.
Abstract: This study investigates the suitability of using plastic,
such as polyethylene terephthalate (PET), as a partial replacement of
natural coarse and fine aggregates (for example, brick chips and
natural sand) to produce lightweight concrete for load bearing
structural members. The plastic coarse aggregate (PCA) and plastic
fine aggregate (PFA) were produced from melted polyethylene
terephthalate (PET) bottles. Tests were conducted using three
different water–cement (w/c) ratios, such as 0.42, 0.48, and 0.57,
where PCA and PFA were used as 50% replacement of coarse and
fine aggregate respectively. Fresh and hardened properties of
concrete have been compared for natural aggregate concrete (NAC),
PCA concrete (PCC) and PFA concrete (PFC). The compressive
strength of concrete at 28 days varied with the water–cement ratio for
both the PCC and PFC. Between PCC and PFC, PFA concrete
showed the highest compressive strength (23.7 MPa) at 0.42 w/c ratio
and also the lowest compressive strength (13.7 MPa) at 0.57 w/c
ratio. Significant reduction in concrete density was mostly observed
for PCC samples, ranging between 1977–1924 kg/m³. With the
increase in water–cement ratio PCC achieved higher workability
compare to both NAC and PFC. It was found that both the PCA and
PFA contained concrete achieved the required compressive strength
to be used for structural purpose as partial replacement of the natural
aggregate; but to obtain the desired lower density as lightweight
concrete the PCA is most suited.
Abstract: A numerical study of natural convection heat transfer
in water filled cavity has been examined in 3-Dfor single phase liquid
cooling system by using an array of parallel plate fins mounted to one
wall of a cavity. The heat generated by a heat source represents a
computer CPU with dimensions of 37.5∗37.5mm mounted on
substrate. A cold plate is used as a heat sink installed on the opposite
vertical end of the enclosure. The air flow inside the computer case is
created by an exhaust fan. A turbulent air flow is assumed and k-ε
model is applied. The fins are installed on the substrate to enhance
the heat transfer. The applied power energy range used is between 15
- 40W. In order to determine the thermal behaviour of the cooling
system, the effect of the heat input and the number of the parallel
plate fins are investigated. The results illustrate that as the fin number
increases the maximum heat source temperature decreases. However,
when the fin number increases to critical value the temperature start
to increase due to the fins are too closely spaced and that cause the
obstruction of water flow. The introduction of parallel plate fins
reduces the maximum heat source temperature by 10% compared to
the case without fins. The cooling system maintains the maximum
chip temperature at 64.68°C when the heat input was at 40W that is
much lower than the recommended computer chips limit temperature
of no more than 85°C and hence the performance of the CPU is
enhanced.
Abstract: Molding process in IC manufacturing secures chips against the harms done by hot, moisture or other external forces. While a chip was being molded,defects like cracks, dilapidation, or voids may be embedding on the molding surface. The molding surfaces the study poises to treat and the ones on the market, though, differ in the surface where texture similar to defects is everywhere. Manual inspection usually passes over low-contrast cracks or voids; hence an automatic optical inspection system for molding surface is necessary. The proposed system is consisted of a CCD, a coaxial light, a back light as well as a motion control unit. Based on the property of statistical textures of the molding surface, a series of digital image processing and classification procedure is carried out. After training of the parameter associated with above algorithm, result of the experiment suggests that the accuracy rate is up to 93.75%, contributing to the inspection quality of IC molding surface.
Abstract: The yield management system is very important to produce high-quality semiconductor chips in the semiconductor manufacturing process. In order to improve quality of semiconductors, various tests are conducted in the post fabrication (FAB) process. During the test process, large amount of data are collected and the data includes a lot of information about defect. In general, the defect on the wafer is the main causes of yield loss. Therefore, analyzing the defect data is necessary to improve performance of yield prediction. The wafer bin map (WBM) is one of the data collected in the test process and includes defect information such as the fail bit patterns. The fail bit has characteristics of spatial point patterns. Therefore, this paper proposes the feature extraction method using the spatial point pattern analysis. Actual data obtained from the semiconductor process is used for experiments and the experimental result shows that the proposed method is more accurately recognize the fail bit patterns.
Abstract: In this study, an local invariant generalized Houghtransform (LI-GHT) method is proposed for integrated circuit (IC) visual positioning. The original generalized Hough transform (GHT) is robust to external noise; however, it is not suitable for visual positioning of IC chips due to the four-dimensionality (4D) of parameter space which leads to the substantial storage requirement and high computational complexity. The proposed LI-GHT method can reduce the dimensionality of parameter space to 2D thanks to the rotational invariance of local invariant geometric feature and it can estimate the accuracy position and rotation angle of IC chips in real-time under noise and blur influence. The experiment results show that the proposed LI-GHT can estimate position and rotation angle of IC chips with high accuracy and fast speed. The proposed LI-GHT algorithm was implemented in IC visual positioning system of radio frequency identification (RFID) packaging equipment.
Abstract: This research is aimed to find optimal values of parameters of acacia wood chips combustion in a bubbling fluidized bed for electrification within the area of the Royal Thai Navy in Sattahip, Chonburi province, Thailand. The size of wood chips falls in the range of 25 mm in diameter. The bed temperature is set within the range of 800±10 oC with the air flow rate of 2.1-3.1 m/min corresponding to the air-fuel ratio between 0.71 to 1.03. The resulting thermal efficiency is approximately 95% with a thermal output of 474.76 kWth, which produced the electricity 0.131 kW-hr.
Abstract: In this work we present a solution for DAGC (Digital
Automatic Gain Control) in WLAN receivers compatible to IEEE 802.11a/g standard. Those standards define communication in 5/2.4
GHz band using Orthogonal Frequency Division Multiplexing OFDM modulation scheme. WLAN Transceiver that we have used
enables gain control over Low Noise Amplifier (LNA) and a
Variable Gain Amplifier (VGA). The control over those signals is
performed in our digital baseband processor using dedicated hardware block DAGC. DAGC in this process is used to automatically control the VGA and LNA in order to achieve better
signal-to-noise ratio, decrease FER (Frame Error Rate) and hold the
average power of the baseband signal close to the desired set point.
DAGC function in baseband processor is done in few steps: measuring power levels of baseband samples of an RF signal,accumulating the differences between the measured power level and
actual gain setting, adjusting a gain factor of the accumulation, and
applying the adjusted gain factor the baseband values. Based on the measurement results of RSSI signal dependence to input power we have concluded that this digital AGC can be implemented applying
the simple linearization of the RSSI. This solution is very simple but also effective and reduces complexity and power consumption of the
DAGC. This DAGC is implemented and tested both in FPGA and in ASIC as a part of our WLAN baseband processor. Finally, we have integrated this circuit in a compact WLAN PCMCIA board based on MAC and baseband ASIC chips designed from us.
Abstract: Designing and implementing intelligent systems has become a crucial factor for the innovation and development of better products of space technologies. A neural network is a parallel system, capable of resolving paradigms that linear computing cannot. Field programmable gate array (FPGA) is a digital device that owns reprogrammable properties and robust flexibility. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than the VLSI and DSP chips. So, many researchers have made great efforts on the realization of neural network (NN) using FPGA technique. In this paper, an introduction of ANN and FPGA technique are briefly shown. Also, Hardware Description Language (VHDL) code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic. Synthesis results for ANN controller are developed using Precision RTL. Proposed VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing ANN. The implementation of multi-layer NN using lookup table LUT reduces the resource utilization for implementation and time for execution.
Abstract: Titanium alloys like Ti-6Al-2Sn-4Zr-6Mo (Ti-
6246) are widely used in aerospace applications. Component
manufacturing, however, is difficult and expensive as their
machinability is extremely poor. A thorough understanding of the
chip formation process is needed to improve related metal cutting
operations.In the current study, orthogonal cutting experiments have
been performed and theresulting chips were analyzed by optical
microscopy and scanning electron microscopy.Chips from aTi-
6246ingot were produced at different cutting speeds and cutting
depths. During the experiments, depending of the cutting conditions,
continuous or segmented chips were formed. Narrow, highly
deformed and grain oriented zones, the so-called shear zone,
separated individual segments. Different material properties have
been measured in the shear zones and the segments.
Abstract: This paper deals with the problem of thermal and
mechanical shocks, which rising during operation, mostly at
interrupted cut. Here will be solved their impact on the cutting edge
tool life, the impact of coating technology on resistance to shocks
and experimental determination of tool life in heating flame.
Resistance of removable cutting edges against thermal and
mechanical shock is an important indicator of quality as well as its
abrasion resistance. Breach of the edge or its crumble may occur due
to cyclic loading. We can observe it not only during the interrupted
cutting (milling, turning areas abandoned hole or slot), but also in
continuous cutting. This is due to the volatility of cutting force on
cutting. Frequency of the volatility in this case depends on the type
of rising chips (chip size element). For difficult-to-machine materials
such as austenitic steel particularly happened at higher cutting speeds
for the localization of plastic deformation in the shear plane and for
the inception of separate elements substantially continuous chips.
This leads to variations of cutting forces substantially greater than for
other types of steel.
Abstract: In this paper, we have compared the performance of a Turbo and Trellis coded optical code division multiple access (OCDMA) system. The comparison of the two codes has been accomplished by employing optical orthogonal codes (OOCs). The Bit Error Rate (BER) performances have been compared by varying the code weights of address codes employed by the system. We have considered the effects of optical multiple access interference (OMAI), thermal noise and avalanche photodiode (APD) detector noise. Analysis has been carried out for the system with and without double optical hard limiter (DHL). From the simulation results it is observed that a better and distinct comparison can be drawn between the performance of Trellis and Turbo coded systems, at lower code weights of optical orthogonal codes for a fixed number of users. The BER performance of the Turbo coded system is found to be better than the Trellis coded system for all code weights that have been considered for the simulation. Nevertheless, the Trellis coded OCDMA system is found to be better than the uncoded OCDMA system. Trellis coded OCDMA can be used in systems where decoding time has to be kept low, bandwidth is limited and high reliability is not a crucial factor as in local area networks. Also the system hardware is less complex in comparison to the Turbo coded system. Trellis coded OCDMA system can be used without significant modification of the existing chipsets. Turbo-coded OCDMA can however be employed in systems where high reliability is needed and bandwidth is not a limiting factor.
Abstract: Metal cutting is a severe plastic deformation process
involving large strains, high strain rates, and high temperatures.
Conventional analysis of the chip formation process is based on bulk
material deformation disregarding the inhomogeneous nature of the
material microstructure. A series of orthogonal cutting tests of AISI
1045 and 1144 steel were conducted which yielded similar process
characteristics and chip formations. With similar shear angles and cut
chip thicknesses, shear strains for both chips were found to range
from 2.0 up to 2.8. The manganese-sulfide (MnS) precipitate in the
1144 steel has a very distinct and uniform shape which allows for
comparison before and after chip formation. From close observations
of MnS precipitates in the cut chips it is shown that the conventional
approach underestimates plastic strains in metal cutting.
Experimental findings revealed local shear strains around a value of
6. These findings and their implications are presented and discussed.
Abstract: Network on a chip (NoC) has been proposed as a viable solution to counter the inefficiency of buses in the current VLSI on-chip interconnects. However, as the silicon chip accommodates more transistors, the probability of transient faults is increasing, making fault tolerance a key concern in scaling chips. In packet based communication on a chip, transient failures can corrupt the data packet and hence, undermine the accuracy of data communication. In this paper, we present a comparative analysis of transient fault tolerant techniques including end-to-end, node-by-node, and stochastic communication based on flooding principle.