Comparative Analysis of Transient-Fault Tolerant Schemes for Network on Chips
Network on a chip (NoC) has been proposed as a viable solution to counter the inefficiency of buses in the current VLSI on-chip interconnects. However, as the silicon chip accommodates more transistors, the probability of transient faults is increasing, making fault tolerance a key concern in scaling chips. In packet based communication on a chip, transient failures can corrupt the data packet and hence, undermine the accuracy of data communication. In this paper, we present a comparative analysis of transient fault tolerant techniques including end-to-end, node-by-node, and stochastic communication based on flooding principle.
[1] Ming Shae Wu and Chung Len Lee, "Using a Periodic Square Wave
Test Signal to Detect Cross Talk Faults", Journal, IEEE Design & Test
of Computers, Volume 22, Issue 2, March-April 2005, pp: 160-169.
[2] Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, N. Vijaykrishnan,
Chita R. Das, "Exploring Fault-Tolerant Network-on-Chip
Architectures", Proceedings of the 2006 International Conference on
Dependable Systems and Networks (DSN06).
[3] P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi,
"Modeling the effect of technology trends on the soft error rate of
combinational logic", In Proceedings of the Dependable Systems and
Networks (DSN), pp: 389-398, 2002.
[4] L. Benini, G. De Micheli, "Networks on Chips: A New SoC Paradigm",
Magazine, IEEE Computer, Jan 2002 Vol.35, No.1, pp.70-78
[5] William J. Dally, Brian Towles, "Route packets, not wires: on-chip
interconnection networks", Proceeding, DAC 2001, pp.684-689
[6] ' Erika Cota, Luigi Carro, Fl'avio Wagner, Marcelo Lubaszewski, "Power
Aware NoC reuse on the testing of core based systems", International
Test Conference ITC 2003, September 30 - Oct 02, 2003, Charlotte NC
USA.
[7] B.W. Johnson, Fault Tolerance, "The Electrical Engineering Handbook",
R.C. Dorf, ed., CRC Press, 1993.
[8] Muhammad Ali, Michael Welzl, Sven Hessler, Sybille Hellebrand:
"A Fault Tolerant Mechanism for handling Permanent and Transient
Failures in a Network on Chip", In Proceedings of the 4th International
Conference on Information Technology : New Generations (IEEE ITNG
2007), Las Vegas, USA, 2-4 April 2007.
[9] Srinivasa R. Sridhara, and Naresh R. Shanbhag, "Coding for Systemon-
Chip Networks: A Unified Framework", IEEE Transactions on very
large scale integration (VLSI) Systems, VOL. 13, NO. 6, JUNE 2005.
[10] D. Bertozzi, L. Benini, Giovanni de Micheli, "Low Power Error Resilient
Encoding for On-Chip Data Buses", Proceedings of the conference on
Design, automation and test in Europe (DATE 2002), 2002, pp: 102,
ISBN:1530-1591.
[11] P. Vellanki, N. Banerjee, and K.S. Chatha, "Quality-of- Service and Error
Control Techniques for Network-on-Chip Architectures", Proceeding of
14th GLSVLSI, Boston, MA, ACM Press, 2004, pp: 45-50.
[12] H. Zimmer and A. Jantsch, "A Fault Model Notation and Error-Control
Scheme for Switch-to-Switch Buses in a Network-on-Chip", Proceedings
of 1st International Conference on Hardware/Software Codesign
and System Synthesis (CODES 03), IEEE Press, 2003, pp: 188-193.
[13] David Bertozzi and Luca Benini, "Xpipes: A Network-on-chip Architecture
for Gigascale System-on-chip". Magazine, IEEE Circuits and
Systems, Second Quarter 2004, pp: 18-31.
[14] Srinivasan Murali, Theocharis Theocharides, N. Vijaykrishnan, Mary
Jane Irwin, Luca Benini, Giovanni De Micheli, "Analysis of Error
Recovery Schemes for Networks on Chips", IEEE Design and Test,
September/October 2005 Vol. 22, No. 5, pp: 434-442.ISSN: 0740-7475.
[15] Dumitras, T.; Marculescu, R. "On-chip stochastic communication",
Proceeding, Design, Automation and Test in Europe Conference and
Exhibition, 2003 Volume , Issue , 2003, pp: 790 - 795.
[16] Karp R. et. al. "Randomized rumor spreading", In Proceedings of the
IEEE Symposium on Foundations of Computer Science, 2000.
[17] M. Millberg, E. Nilsson, R. Thid, S. Kumar, A. Jantsch, "The Nostrum
backbonea communication protocol stack for networks on chip", In VLSI
Design Conference, Mumbai, India, January 2004.
[18] http://www.isi.edu/nsnam/ns/
[19] Vu-Duc Ngo, Hae-Wook Choi, "On Chip Network: Topology design
and evaluation using NS2", In Proceedings of the 7th International
Conference on Advanced Communication Technology (ICACT 2005),
Phoenix Park, Korea, Feb. 21-23, 2005.
[20] Y.-R. Sun, S. Kumar, and A. Jantsch, "Simulation and evaluation of a
network on chip architecture using ns-2", In Proceedings of the IEEE
NorChip Conference, November 2002.
[21] Alireza Vahdatpour, Ahmadreza Tavakoli, Mohammad Hossein Falaki,
"Hierarchical Graph: A New Cost Effective Architecture for Network
on Chip", In Proceedings of the International Conference on Embedded
And Ubiquitous Computing, Nagasaki, Japan, December 2005.
[22] Franco Fummi, Giovanni Perbellini, Paolo Gallo, Massimo Poncino,
Stefano Martini and Fabio Ricciato, "A Timing-Accurate Modeling
and Simulation Environment for Networked Embedded Systems", In
Proceedings of the 40th Design Automation Conference (DAC), USA,
June 2-6, 2003.
[1] Ming Shae Wu and Chung Len Lee, "Using a Periodic Square Wave
Test Signal to Detect Cross Talk Faults", Journal, IEEE Design & Test
of Computers, Volume 22, Issue 2, March-April 2005, pp: 160-169.
[2] Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, N. Vijaykrishnan,
Chita R. Das, "Exploring Fault-Tolerant Network-on-Chip
Architectures", Proceedings of the 2006 International Conference on
Dependable Systems and Networks (DSN06).
[3] P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi,
"Modeling the effect of technology trends on the soft error rate of
combinational logic", In Proceedings of the Dependable Systems and
Networks (DSN), pp: 389-398, 2002.
[4] L. Benini, G. De Micheli, "Networks on Chips: A New SoC Paradigm",
Magazine, IEEE Computer, Jan 2002 Vol.35, No.1, pp.70-78
[5] William J. Dally, Brian Towles, "Route packets, not wires: on-chip
interconnection networks", Proceeding, DAC 2001, pp.684-689
[6] ' Erika Cota, Luigi Carro, Fl'avio Wagner, Marcelo Lubaszewski, "Power
Aware NoC reuse on the testing of core based systems", International
Test Conference ITC 2003, September 30 - Oct 02, 2003, Charlotte NC
USA.
[7] B.W. Johnson, Fault Tolerance, "The Electrical Engineering Handbook",
R.C. Dorf, ed., CRC Press, 1993.
[8] Muhammad Ali, Michael Welzl, Sven Hessler, Sybille Hellebrand:
"A Fault Tolerant Mechanism for handling Permanent and Transient
Failures in a Network on Chip", In Proceedings of the 4th International
Conference on Information Technology : New Generations (IEEE ITNG
2007), Las Vegas, USA, 2-4 April 2007.
[9] Srinivasa R. Sridhara, and Naresh R. Shanbhag, "Coding for Systemon-
Chip Networks: A Unified Framework", IEEE Transactions on very
large scale integration (VLSI) Systems, VOL. 13, NO. 6, JUNE 2005.
[10] D. Bertozzi, L. Benini, Giovanni de Micheli, "Low Power Error Resilient
Encoding for On-Chip Data Buses", Proceedings of the conference on
Design, automation and test in Europe (DATE 2002), 2002, pp: 102,
ISBN:1530-1591.
[11] P. Vellanki, N. Banerjee, and K.S. Chatha, "Quality-of- Service and Error
Control Techniques for Network-on-Chip Architectures", Proceeding of
14th GLSVLSI, Boston, MA, ACM Press, 2004, pp: 45-50.
[12] H. Zimmer and A. Jantsch, "A Fault Model Notation and Error-Control
Scheme for Switch-to-Switch Buses in a Network-on-Chip", Proceedings
of 1st International Conference on Hardware/Software Codesign
and System Synthesis (CODES 03), IEEE Press, 2003, pp: 188-193.
[13] David Bertozzi and Luca Benini, "Xpipes: A Network-on-chip Architecture
for Gigascale System-on-chip". Magazine, IEEE Circuits and
Systems, Second Quarter 2004, pp: 18-31.
[14] Srinivasan Murali, Theocharis Theocharides, N. Vijaykrishnan, Mary
Jane Irwin, Luca Benini, Giovanni De Micheli, "Analysis of Error
Recovery Schemes for Networks on Chips", IEEE Design and Test,
September/October 2005 Vol. 22, No. 5, pp: 434-442.ISSN: 0740-7475.
[15] Dumitras, T.; Marculescu, R. "On-chip stochastic communication",
Proceeding, Design, Automation and Test in Europe Conference and
Exhibition, 2003 Volume , Issue , 2003, pp: 790 - 795.
[16] Karp R. et. al. "Randomized rumor spreading", In Proceedings of the
IEEE Symposium on Foundations of Computer Science, 2000.
[17] M. Millberg, E. Nilsson, R. Thid, S. Kumar, A. Jantsch, "The Nostrum
backbonea communication protocol stack for networks on chip", In VLSI
Design Conference, Mumbai, India, January 2004.
[18] http://www.isi.edu/nsnam/ns/
[19] Vu-Duc Ngo, Hae-Wook Choi, "On Chip Network: Topology design
and evaluation using NS2", In Proceedings of the 7th International
Conference on Advanced Communication Technology (ICACT 2005),
Phoenix Park, Korea, Feb. 21-23, 2005.
[20] Y.-R. Sun, S. Kumar, and A. Jantsch, "Simulation and evaluation of a
network on chip architecture using ns-2", In Proceedings of the IEEE
NorChip Conference, November 2002.
[21] Alireza Vahdatpour, Ahmadreza Tavakoli, Mohammad Hossein Falaki,
"Hierarchical Graph: A New Cost Effective Architecture for Network
on Chip", In Proceedings of the International Conference on Embedded
And Ubiquitous Computing, Nagasaki, Japan, December 2005.
[22] Franco Fummi, Giovanni Perbellini, Paolo Gallo, Massimo Poncino,
Stefano Martini and Fabio Ricciato, "A Timing-Accurate Modeling
and Simulation Environment for Networked Embedded Systems", In
Proceedings of the 40th Design Automation Conference (DAC), USA,
June 2-6, 2003.
@article{"International Journal of Information, Control and Computer Sciences:59751", author = "Muhammad Ali and Awais Adnan", title = "Comparative Analysis of Transient-Fault Tolerant Schemes for Network on Chips", abstract = "Network on a chip (NoC) has been proposed as a viable solution to counter the inefficiency of buses in the current VLSI on-chip interconnects. However, as the silicon chip accommodates more transistors, the probability of transient faults is increasing, making fault tolerance a key concern in scaling chips. In packet based communication on a chip, transient failures can corrupt the data packet and hence, undermine the accuracy of data communication. In this paper, we present a comparative analysis of transient fault tolerant techniques including end-to-end, node-by-node, and stochastic communication based on flooding principle.
", keywords = "NoC, fault-tolerance, transient faults.", volume = "2", number = "7", pages = "2491-6", }
