Shelf Life Extension of Milk Pomade Sweet – Sherbet with Crunchy Peanut Chips by MAP in Various Packaging Materials

The objective of the research was to evaluate the hardness stability of milk pomade sweets packed in several packaging materials (OPP, Multibarrier 60 HFP, BIALON 65 HFP, BIALON 50 HFP, ECOLEAN) by several packaging technologies – modified atmosphere (MAP) (consisting of 30% CO2+70% N2; 30% N2+70% CO2 and 100% CO2) and control – in air ambiance. Samples were stored at the room temperature +21±1 °C. The studies of the samples were carried out before packaging and after 2, 4, 6, 8, and 10 storage weeks.

Performance Trade-Off of File System between Overwriting and Dynamic Relocation on a Solid State Drive

Most file systems overwrite modified file data and metadata in their original locations, while the Log-structured File System (LFS) dynamically relocates them to other locations. We design and implement the Evergreen file system that can select between overwriting or relocation for each block of a file or metadata. Therefore, the Evergreen file system can achieve superior write performance by sequentializing write requests (similar to LFS-style relocation) when space utilization is low and overwriting when utilization is high. Another challenging issue is identifying performance benefits of LFS-style relocation over overwriting on a newly introduced SSD (Solid State Drive) which has only Flash-memory chips and control circuits without mechanical parts. Our experimental results measured on a SSD show that relocation outperforms overwriting when space utilization is below 80% and vice versa.

A Clock Skew Minimization Technique Considering Temperature Gradient

The trend of growing density on chips has increases not only the temperature in chips but also the gradient of the temperature depending on locations. In this paper, we propose the balanced skew tree generation technique for minimizing the clock skew that is affected by the temperature gradients on chips. We calculate the interconnect delay using Elmore delay equation, and find out the optimal balanced clock tree by modifying the clock trees generated through the Deferred Merge Embedding(DME) algorithm. The experimental results show that the distance variance of clock insertion points with and without considering the temperature gradient can be lowered below 54% and we confirm that the skew is remarkably decreased after applying the proposed technique.

An Ant-based Clustering System for Knowledge Discovery in DNA Chip Analysis Data

Biological data has several characteristics that strongly differentiate it from typical business data. It is much more complex, usually large in size, and continuously changes. Until recently business data has been the main target for discovering trends, patterns or future expectations. However, with the recent rise in biotechnology, the powerful technology that was used for analyzing business data is now being applied to biological data. With the advanced technology at hand, the main trend in biological research is rapidly changing from structural DNA analysis to understanding cellular functions of the DNA sequences. DNA chips are now being used to perform experiments and DNA analysis processes are being used by researchers. Clustering is one of the important processes used for grouping together similar entities. There are many clustering algorithms such as hierarchical clustering, self-organizing maps, K-means clustering and so on. In this paper, we propose a clustering algorithm that imitates the ecosystem taking into account the features of biological data. We implemented the system using an Ant-Colony clustering algorithm. The system decides the number of clusters automatically. The system processes the input biological data, runs the Ant-Colony algorithm, draws the Topic Map, assigns clusters to the genes and displays the output. We tested the algorithm with a test data of 100 to1000 genes and 24 samples and show promising results for applying this algorithm to clustering DNA chip data.

The Suitability of Potato Cultivars in Production of Chips and Sticks by Using Microwave-Vacuum Drier

The aim of present experiment was to evaluate the influence of cultivar to quality parameters of dried potato chips and sticks produced in microwave-vacuum drier. The potatoes before drying were blanched in oil and water at 180ºC and at 85ºC respectively. The moisture content, crispiness, the colour (CIE L*a*b*), the content of ascorbic acid, total carotenoids and total fat content of dried potato chips and sticks was determined The highest ascorbic acid content, high content of carotenoids, low total fat content, low acrylamide content and good crispiness (low breaking force) especially for sticks was determined in the samples of Gundega cultivar.

Analysis of Acoustic Emission Signal for the Detection of Defective Manufactures in Press Process

Small cracks or chips of a product appear very frequently in the course of continuous production of an automatic press process system. These phenomena become the cause of not only defective product but also damage of a press mold. In order to solve this problem AE system was introduced. AE system was expected to be very effective to real time detection of the defective product and to prevention of the damage of the press molds. In this study, for pick and analysis of AE signals generated from the press process, AE sensors/pre-amplifier/analysis and processing board were used as frequently found in the other similar cases. For analysis and processing the AE signals picked in real time from the good or bad products, specialized software called cdm8 was used. As a result of this work it was conformed that intensity and shape of the various AE signals differ depending on the weight and thickness of metal sheet and process type.

Chip Formation during Turning Multiphase Microalloyed Steel

Machining through turning was carried out in a lathe to study the chip formation of Multiphase Ferrite (F-B-M) microalloyed steel. Taguchi orthogonal array was employed to perform the machining. Continuous and discontinuous chips were formed for different cutting parameters like speed, feed and depth of cut. Optical and scanning electron microscope was employed to identify the chip morphology.

Machining of FRP Composites by Abrasive Jet Machining Optimization Using Taguchi

Abrasive Jet Machining is an Unconventional machining process in which the metal is removed from brittle and hard material in the form of micro-chips. With increase in need of materials like ceramics, composites, in manufacturing of various Mechanical & Electronic components, AJM has become a useful technique for micro machining. The present study highlights the influence of different parameters like Pressure, SOD, Time, Abrasive grain size, nozzle diameter on the Metal removal of FRP (Fiber Reinforced Polymer) composite by Abrasive jet machining. The results of the Experiments conducted were analyzed and optimized with TAGUCHI method of Optimization and ANOVA for Optimal Value.

Performance Evaluation of a Neural Network based General Purpose Space Vector Modulator

Space Vector Modulation (SVM) is an optimum Pulse Width Modulation (PWM) technique for an inverter used in a variable frequency drive applications. It is computationally rigorous and hence limits the inverter switching frequency. Increase in switching frequency can be achieved using Neural Network (NN) based SVM, implemented on application specific chips. This paper proposes a neural network based SVM technique for a Voltage Source Inverter (VSI). The network proposed is independent of switching frequency. Different architectures are investigated keeping the total number of neurons constant. The performance of the inverter is compared for various switching frequencies for different architectures of NN based SVM. From the results obtained, the network with minimum resource and appropriate word length is identified. The bit precision required for this application is identified. The network with 8-bit precision is implemented in the IC XCV 400 and the results are presented. The performance of NN based general purpose SVM with higher bit precision is discussed.

Implementation of Adder-Subtracter Design with VerilogHDL

According to the density of the chips, designers are trying to put so any facilities of computational and storage on single chips. Along with the complexity of computational and storage circuits, the designing, testing and debugging become more and more complex and expensive. So, hardware design will be built by using very high speed hardware description language, which is more efficient and cost effective. This paper will focus on the implementation of 32-bit ALU design based on Verilog hardware description language. Adder and subtracter operate correctly on both unsigned and positive numbers. In ALU, addition takes most of the time if it uses the ripple-carry adder. The general strategy for designing fast adders is to reduce the time required to form carry signals. Adders that use this principle are called carry look- ahead adder. The carry look-ahead adder is to be designed with combination of 4-bit adders. The syntax of Verilog HDL is similar to the C programming language. This paper proposes a unified approach to ALU design in which both simulation and formal verification can co-exist.

A New Design of Mobile Thermoelectric Power Generation System

This paper presents a compact thermoelectric power generator system based on temperature difference across the element. The system can transfer the burning heat energy to electric energy directly. The proposed system has a thermoelectric generator and a power control box. In the generator, there are 4 thermoelectric modules (TEMs), each of which uses 2 thermoelectric chips (TEs) and 2 cold sinks, 1 thermal absorber, and 1 thermal conduction flat board. In the power control box, there are 1 storing energy device, 1 converter, and 1 inverter. The total net generating power is about 11W. This system uses commercial portable gas stoves or burns timber or the coal as the heat source, which is easily obtained. It adopts solid-state thermoelectric chips as heat inverter parts. The system has the advantages of being light-weight, quite, and mobile, requiring no maintenance, and havng easily-supplied heat source. The system can be used a as long as burning is allowed. This system works well for highly-mobilized outdoors situations by providing a power for illumination, entertainment equipment or the wireless equipment at refuge. Under heavy storms such as typhoon, when the solar panels become ineffective and the wind-powered machines malfunction, the thermoelectric power generator can continue providing the vital power.

Fluidity of A713 Cast Alloy with and without Scrap Addition using Double Spiral Fluidity Test: A Comparison

Recycling of aluminum alloys often decrease fluidity, consequently influence the castability of the alloy. In this study, the fluidity of Al-Zn alloys, such as the standard A713 alloy with and without scrap addition has been investigated. The scrap added was comprised of contaminated alloy turning chips. Fluidity measurements were performed with double spiral fluidity test consisting of gravity casting of double spirals in green sand moulds with good reproducibility. The influence of recycled alloy on fluidity has been compared with that of the virgin alloy and the results showed that the fluidity decreased with the increase in recycled alloy at minimum pouring temperatures. Interestingly, an appreciable improvement in the fluidity was observed at maximum pouring temperature, especially for coated spirals.

Performance Analysis of QS-CDMA Systems

In the paper, the performance of quasi-synchronous CDMA (QS-CDMA) system, which can allow an increased timing error in synchronized access, is discussed. Average BER performance of the system is analyzed in the condition of different access timing error and different asynchronous users by simulation in AWGN channel. The results show that QS-CDMA system is shown to have great performance gain over the asynchronous system when access timing error is within a few chips and asynchronous users is tolerable. However, with access timing error increasing and asynchronous users increasing, the performance of QS-CDMA will degrade. Also, we can determine the number of tolerable asynchronous users for different access timing error by simulation figures.

GridNtru: High Performance PKCS

Cryptographic algorithms play a crucial role in the information society by providing protection from unauthorized access to sensitive data. It is clear that information technology will become increasingly pervasive, Hence we can expect the emergence of ubiquitous or pervasive computing, ambient intelligence. These new environments and applications will present new security challenges, and there is no doubt that cryptographic algorithms and protocols will form a part of the solution. The efficiency of a public key cryptosystem is mainly measured in computational overheads, key size and bandwidth. In particular the RSA algorithm is used in many applications for providing the security. Although the security of RSA is beyond doubt, the evolution in computing power has caused a growth in the necessary key length. The fact that most chips on smart cards can-t process key extending 1024 bit shows that there is need for alternative. NTRU is such an alternative and it is a collection of mathematical algorithm based on manipulating lists of very small integers and polynomials. This allows NTRU to high speeds with the use of minimal computing power. NTRU (Nth degree Truncated Polynomial Ring Unit) is the first secure public key cryptosystem not based on factorization or discrete logarithm problem. This means that given sufficient computational resources and time, an adversary, should not be able to break the key. The multi-party communication and requirement of optimal resource utilization necessitated the need for the present day demand of applications that need security enforcement technique .and can be enhanced with high-end computing. This has promoted us to develop high-performance NTRU schemes using approaches such as the use of high-end computing hardware. Peer-to-peer (P2P) or enterprise grids are proven as one of the approaches for developing high-end computing systems. By utilizing them one can improve the performance of NTRU through parallel execution. In this paper we propose and develop an application for NTRU using enterprise grid middleware called Alchemi. An analysis and comparison of its performance for various text files is presented.

Classifying Bio-Chip Data using an Ant Colony System Algorithm

Bio-chips are used for experiments on genes and contain various information such as genes, samples and so on. The two-dimensional bio-chips, in which one axis represent genes and the other represent samples, are widely being used these days. Instead of experimenting with real genes which cost lots of money and much time to get the results, bio-chips are being used for biological experiments. And extracting data from the bio-chips with high accuracy and finding out the patterns or useful information from such data is very important. Bio-chip analysis systems extract data from various kinds of bio-chips and mine the data in order to get useful information. One of the commonly used methods to mine the data is classification. The algorithm that is used to classify the data can be various depending on the data types or number characteristics and so on. Considering that bio-chip data is extremely large, an algorithm that imitates the ecosystem such as the ant algorithm is suitable to use as an algorithm for classification. This paper focuses on finding the classification rules from the bio-chip data using the Ant Colony algorithm which imitates the ecosystem. The developed system takes in consideration the accuracy of the discovered rules when it applies it to the bio-chip data in order to predict the classes.

Development of Electric Performance Testing System for Ceramic Chips using PZT Actuator

Reno-pin contact test is a method that is controlled by DC motor used to characterize electronic chips. This method is used in electronic and telecommunication devices. A new electric performance testing system is developed in which the testing method is controlled by using Piezoelectric Transducer (PZT) instead of DC motor which reduces vibration and noise. The vertical displacement of the Reno-pin is very short in the Reno-pin contact testing system. Now using a flexible guide in the new Reno-pin contact system, the vertical movement of the Reno-pin is increased many times of the existing Reno-pin contact testing method using DC motor. Using the present electric performance testing system with a flexible hinge and PZT instead of DC motor, manufacturing of electronic chips are able to characterize chips with low cost and high speed.

Encoding and Compressing Data for Decreasing Number of Switches in Baseline Networks

This method decrease usage power (expenditure) in networks on chips (NOC). This method data coding for data transferring in order to reduces expenditure. This method uses data compression reduces the size. Expenditure calculation in NOC occurs inside of NOC based on grown models and transitive activities in entry ports. The goal of simulating is to weigh expenditure for encoding, decoding and compressing in Baseline networks and reduction of switches in this type of networks. KeywordsNetworks on chip, Compression, Encoding, Baseline networks, Banyan networks.