Abstract: The trend of growing density on chips has increases not
only the temperature in chips but also the gradient of the temperature
depending on locations. In this paper, we propose the balanced skew
tree generation technique for minimizing the clock skew that is
affected by the temperature gradients on chips. We calculate the
interconnect delay using Elmore delay equation, and find out the
optimal balanced clock tree by modifying the clock trees generated
through the Deferred Merge Embedding(DME) algorithm. The
experimental results show that the distance variance of clock insertion
points with and without considering the temperature gradient can be
lowered below 54% and we confirm that the skew is remarkably
decreased after applying the proposed technique.