Abstract: In this paper, we present and investigate a double gate PN diode based tunnel field effect transistor (DGPNTFET). The importance of proposed structure is that the formation of different drain doping is not required and ambipolar effect in OFF state is completely removed for this structure. Validation of this structure to behave like a Tunnel Field Effect Transistor (TFET) is carried out through energy band diagrams and transfer characteristics. Simulated result shows point subthreshold slope (SS) of 19.14 mV/decade and ON to OFF current ratio (ION / IOFF) of 2.66 × 1014 (ION at VGS=1.5V, VDS=1V and IOFF at VGS=0V, VDS=1V) for gate length of 20nm and HfO2 as gate oxide at room temperature. Which indicate that the DGPNTFET is a promising candidate for nano-scale, ambipolar free switch.
Abstract: The paper presents a simulation study of the electrical
characteristic of Bulk Planar Junctionless Transistor (BPJLT) using
spacer. The BPJLT is a transistor without any PN junctions in the
vertical direction. It is a gate controlled variable resistor. The
characteristics of BPJLT are analyzed by varying the oxide material
under the gate. It can be shown from the simulation that an ideal
subthreshold slope of ~60 mV/decade can be achieved by using highk
dielectric. The effects of variation of spacer length and material on
the electrical characteristic of BPJLT are also investigated in the
paper. The ION / IOFF ratio improvement is of the order of 107 and the
OFF current reduction of 10-4 is obtained by using gate dielectric of
HfO2 instead of SiO2.
Abstract: Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to suppress various short channel effect problems. The gate to channel coupling in vertical DG-MOSFET are doubled, thus resulting in higher current density. By having two gates, both gates are able to control the channel from both sides and possess better electrostatic control over the channel. In order to ensure that the transistor possess a superb turn-off characteristic, the subs-threshold swing (SS) must be kept at minimum value (60-90mV/dec). By utilizing SILVACO TCAD software, an n-channel vertical DG-MOSFET was successfully designed while keeping the sub-threshold swing (SS) value as minimum as possible. From the observation made, the value of sub-threshold swing (SS) was able to be varied by adjusting the height of the silicon pillar. The minimum value of sub-threshold swing (SS) was found to be 64.7mV/dec with threshold voltage (VTH) of 0.895V. The ideal height of the vertical DG-MOSFET pillar was found to be at 0.265 µm.
Abstract: The integrity and issues related to electrostatic performance associated with scaling Si MOSFET bulk sub 10nm channel length promotes research in new device architectures such as SOI, double gate and GAA MOSFET. In this paper, we present some novel characteristic of horizontal rectangular gate\gate all around MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some parameters variation on our structure, that having a direct impact on their threshold voltage and drain current. In addition, our TFET showed reasonable ION/IOFF ratio of (104) and low drain induced barrier lowering (DIBL) of 39 mV/V.
Abstract: In this paper electrical characteristics of various kinds
of multiple-gate silicon nanowire transistors (SNWT) with the
channel length equal to 7 nm are compared. A fully ballistic quantum
mechanical transport approach based on NEGF was employed to
analyses electrical characteristics of rectangular and cylindrical
silicon nanowire transistors as well as a Double gate MOS FET. A
double gate, triple gate, and gate all around nano wires were studied
to investigate the impact of increasing the number of gates on the
control of the short channel effect which is important in nanoscale
devices. Also in the case of triple gate rectangular SNWT inserting
extra gates on the bottom of device can improve the application of
device. The results indicate that by using gate all around structures
short channel effects such as DIBL, subthreshold swing and delay
reduces.