Performance Analysis of BPJLT with Different Gate and Spacer Materials

The paper presents a simulation study of the electrical
characteristic of Bulk Planar Junctionless Transistor (BPJLT) using
spacer. The BPJLT is a transistor without any PN junctions in the
vertical direction. It is a gate controlled variable resistor. The
characteristics of BPJLT are analyzed by varying the oxide material
under the gate. It can be shown from the simulation that an ideal
subthreshold slope of ~60 mV/decade can be achieved by using highk
dielectric. The effects of variation of spacer length and material on
the electrical characteristic of BPJLT are also investigated in the
paper. The ION / IOFF ratio improvement is of the order of 107 and the
OFF current reduction of 10-4 is obtained by using gate dielectric of
HfO2 instead of SiO2.

Authors:

• Porag Jyoti Ligira
• Gargi Khanna

Keywords:

• BPJLT
• double gate
• high-k
• spacer.

References:

[1] J. E. Lilienfeld, “Method and apparatus for controlling electric
current,”U.S. Patent 1 745 175, Oct. 22, 1925.
[2] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P.
Colinge, “Junctionless multigate field-effect transistor,” Appl. Phys.
Lett., vol. 94, no. 5, pp. 053511-1–053511-2, Feb. 2009.
[3] J.-P. Colinge et al., “Nanowire resistors without junctions,” Nat.
Nanotechnology., vol. 5, no. 3, pp. 225–229, Mar. 2010.
[4] A. Kranti et al., “Junctionless nanowire transistor: Properties and design
guidelines,” IEEE 34th Eur. Solid-State Device Res. Conf., pp. 357–360,
Aug. 2010.
[5] S. Gundapaneni, M. Bajaj, R. K. Pandey, K. V. R. Murali,S. Ganguly,
and A. Kottantharayil, “Effect of band-to-band tunneling on Junctionless
transistors,” IEEE Trans. Electron Devices, vol. 59, no. 4,pp. 1023–
1029, Apr. 2012.
[6] R.K. Baruah, R.P. Paily, “Estimation of process-induced variations in
double-gate Junctionless transistor“, CODEC, IEEE International
Conference, pp.1-4, 2012.
[7] B. Ghosh and M. W. Akram, “Junctionless Tunnel Field Effect
Transistor”, IEEE electron device letters, vol. 34, no. 5, 2013.
[8] B. Ghosh, P. Bal, P. Mondol, “A junctionless tunnel field effect
transistor with low subthreshold slope”, Springer , Journal of
Computational Electronics, vol. 12, no. 3, pp.428-436, 2013.
[9] Sentaurus Device User Guide, Synopsys, Inc. Mountain View, CA,
2008.