Abstract: This paper reports on the impact study with the variation of the gate insulation material and thickness on different models of pocket implanted sub-100 nm n-MOS device. The gate materials used here are silicon dioxide (SiO2), aluminum silicate (Al2SiO5), silicon nitride (Si3N4), alumina (Al2O3), hafnium silicate (HfSiO4), tantalum pentoxide (Ta2O5), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and lanthanum oxide (La2O3) upon a p-type silicon substrate material. The gate insulation thickness was varied from 2.0 nm to 3.5 nm for a 50 nm channel length pocket implanted n-MOSFET. There are several models available for this device. We have studied and simulated threshold voltage model incorporating drain and substrate bias effects, surface potential, inversion layer charge, pinch-off voltage, effective electric field, inversion layer mobility, and subthreshold drain current models based on two linear symmetric pocket doping profiles. We have changed the values of the two parameters, viz. gate insulation material and thickness gradually fixing the other parameter at their typical values. Then we compared and analyzed the simulation results. This study would be helpful for the nano-scaled MOS device designers for various applications to predict the device behavior.
Abstract: The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.
Abstract: Fast neutron irradiation using nuclear reactors is an effective method to improve switching loss and short circuit durability of power semiconductor (insulated gate bipolar transistors (IGBT) and insulated gate transistors (IGT), etc.). However, not only fast neutrons but also thermal neutrons, epithermal neutrons and gamma exist in the nuclear reactor. And the electrical properties of the IGBT may be deteriorated by the irradiation of gamma. Gamma irradiation damages are known to be caused by Total Ionizing Dose (TID) effect and Single Event Effect (SEE), Displacement Damage. Especially, the TID effect deteriorated the electrical properties such as leakage current and threshold voltage of a power semiconductor. This work can confirm the effect of the gamma irradiation on the electrical properties of 600 V NPT-IGBT. Irradiation of gamma forms lattice defects in the gate oxide and Si-SiO2 interface of the IGBT. It was confirmed that this lattice defect acts on the center of the trap and affects the threshold voltage, thereby negatively shifted the threshold voltage according to TID. In addition to the change in the carrier mobility, the conductivity modulation decreases in the n-drift region, indicating a negative influence that the forward voltage drop decreases. The turn-off delay time of the device before irradiation was 212 ns. Those of 2.5, 10, 30, 70 and 100 kRad(Si) were 225, 258, 311, 328, and 350 ns, respectively. The gamma irradiation increased the turn-off delay time of the IGBT by approximately 65%, and the switching characteristics deteriorated.
Abstract: The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from ID-VG characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.
Abstract: The results of the studies for the hydrogen production by the application of water electrolysis and plasma-chemical processing of gas condensate-waste of natural gas production methods are presented. Thin coating covers the electrode surfaces in the process of water electrolysis. Therefore, water for electrolysis was first exposed to electrosedimentation. The threshold voltage is shifted to a lower value compared with the use of electrodes made of stainless steel. At electrolysis of electrosedimented water by use of electrodes from stainless steel, a significant amount of hydrogen is formed. Pyrolysis of gas condensates in the atmosphere of a nitrogen was followed by the formation of acetylene (3-7 vol.%), ethylene (4-8 vol.%), and pyrolysis carbon (10-15 wt.%).
Abstract: Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However, thorough understanding of this reliability failure mechanism is still unachievable due to a recovery characteristic known as NBTI recovery. This paper will demonstrate the severity of NBTI recovery as well as one of the effective methods used to mitigate, which is the minimization of measurement system delays. Comparison was done in between two measurement systems that have significant differences in measurement delays to show how NBTI recovery causes result deviations and how fast measurement systems can mitigate NBTI recovery. Another method to minimize NBTI recovery without the influence of measurement system known as Fast Wafer Level Reliability (FWLR) NBTI was also done to be used as reference.
Abstract: In order to manufacture short gap single Si nanowire
(NW) field effect transistor (FET) by imprinting and transferring
method, we introduce the method using Al2O3 sacrificial layer. The
diameters of cylindrical Si NW addressed between Au electrodes by
dielectrophoretic (DEP) alignment method are controlled to 106, 128,
and 148 nm. After imprinting and transfer process, cylindrical Si NW
is embedded in PVP adhesive and dielectric layer. By curing
transferred cylindrical Si NW and Au electrodes on PVP-coated p++ Si
substrate with 200nm-thick SiO2, 3μm gap Si NW FET fabrication
was completed. As the diameter of embedded Si NW increases, the
mobility of FET increases from 80.51 to 121.24 cm2/V·s and the
threshold voltage moves from –7.17 to –2.44 V because the ratio of
surface to volume gets reduced.
Abstract: The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.
Abstract: Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-Vt transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.
Abstract: An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.
Abstract: Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.
Abstract: In this study we present the effect of elevated
temperatures from 300K to 400K on the electrical properties of
copper Phthalocyanine (CuPc) based organic field effect transistors
(OFET). Thin films of organic semiconductor CuPc (40nm) and
semitransparent Al (20nm) were deposited in sequence, by vacuum
evaporation on a glass substrate with previously deposited Ag source
and drain electrodes with a gap of 40 μm. Under resistive mode of
operation, where gate was suspended it was observed that drain
current of this organic field effect transistor (OFET) show an
increase with temperature. While in grounded gate condition metal
(aluminum) – semiconductor (Copper Phthalocyanine) Schottky
junction dominated the output characteristics and device showed
switching effect from low to high conduction states like Zener diode
at higher bias voltages. This threshold voltage for switching effect
has been found to be inversely proportional to temperature and shows
an abrupt decrease after knee temperature of 360K. Change in
dynamic resistance (Rd = dV/dI) with respect to temperature was
observed to be -1%/K.
Abstract: This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.
Abstract: A high precision temperature insensitive current and voltage reference generator is presented. It is specifically developed for temperature compensated oscillator. The circuit, designed using MXIC 0.5um CMOS technology, has an operating voltage that ranges from 2.6V to 5V and generates a voltage of 1.21V and a current of 6.38 ӴA. It exhibits a variation of ±0.3nA for the current reference and a stable output for voltage reference as the temperature is varied from 0°C to 70°C. The power supply rejection ratio obtained without any filtering capacitor at 100Hz and 10MHz is -30dB and -12dB respectively.
Abstract: This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poisson-s equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The simulated result is compared with the two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Abstract: We fabricated the inverted-staggered etch stopper
structure oxide-based TFT and investigated the characteristics of oxide
TFT under the 400 nm wavelength light illumination. When 400 nm
light was illuminated, the threshold voltage (Vth) decreased and
subthreshold slope (SS) increased at forward sweep, while Vth and SS
were not altered when larger wavelength lights, such as 650 nm, 550
nm and 450 nm, were illuminated. At reverse sweep, the transfer curve
barely changed even under 400 nm light. Our experimental results
support that photo-induced hole carriers are captured by donor-like
interface trap and it caused the decrease of Vth and increase of SS. We
investigated the interface trap density increases proportionally to the
photo-induced hole concentration at active layer.
Abstract: This paper presents a low-voltage low-power differential linear transconductor with near rail-to-rail input swing. Based on the current-mirror OTA topology, the proposed transconductor combines the Flipped Voltage Follower (FVF) technique to linearize the transconductor behavior that leads to class- AB linear operation and the virtual transistor technique to lower the effective threshold voltages of the transistors which offers an advantage in terms of low supply requirement. Design of the OTA has been discussed. It operates at supply voltages of about ±0.8V. Simulation results for 0.18μm TSMC CMOS technology show a good input range of 1Vpp with a high DC gain of 81.53dB and a total harmonic distortion of -40dB at 1MHz for an input of 1Vpp. The main aim of this paper is to present and compare new OTA design with high transconductance, which has a potential to be used in low voltage applications.
Abstract: We have fabricated a-IGZO TFT and investigated the
stability under positive DC and AC bias stress. The threshold voltage
of a-IGZO TFT shifts positively under those biases, and that reduces
on-current. For this reason, conventional shift-register circuit
employing TFTs which stressed by positive bias will be unstable, may
do not work properly. We have designed a new 6-transistor
shift-register, which has less transistors than prior circuits. The TFTs
of the proposed shift-register are not suffering from positive DC or AC
stress, mainly kept unbiased. Despite the compact design, the stable
output signal was verified through the SPICE simulation even under
RC delay of clock signal.
Abstract: Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to suppress various short channel effect problems. The gate to channel coupling in vertical DG-MOSFET are doubled, thus resulting in higher current density. By having two gates, both gates are able to control the channel from both sides and possess better electrostatic control over the channel. In order to ensure that the transistor possess a superb turn-off characteristic, the subs-threshold swing (SS) must be kept at minimum value (60-90mV/dec). By utilizing SILVACO TCAD software, an n-channel vertical DG-MOSFET was successfully designed while keeping the sub-threshold swing (SS) value as minimum as possible. From the observation made, the value of sub-threshold swing (SS) was able to be varied by adjusting the height of the silicon pillar. The minimum value of sub-threshold swing (SS) was found to be 64.7mV/dec with threshold voltage (VTH) of 0.895V. The ideal height of the vertical DG-MOSFET pillar was found to be at 0.265 µm.
Abstract: Wall-surface jet induced by the dielectric barrier
discharge (DBD) has been proposed as an actuator for active flow
control in aerodynamic applications. Discharge plasma evolution of
the DBD plasma actuator was simulated based on a simple fluid model,
in which the electron, one type of positive ion and negative ion were
taken into account. Two-dimensional simulation was conducted, and
the results are in agreement with the insights obtained from
experimental studies. The simulation results indicate that the discharge
mode changes depending on applied voltage slope; when the applied
voltage is positive-going with high applied voltage slope, the
corona-type discharge mode turns into the streamer-type discharge
mode and the threshold voltage slope is around 300 kV/ms in this
simulation. The characteristics of the electrohydrodynamic (EHD)
force, which is the source of the wall-surface jet, also change
depending on the discharge mode; the tentative peak value of the EHD
force during the positive-going voltage phase is saturated by the
periodical formation of the streamer-type discharge.