Abstract: Triple-Level Cell (TLC) NAND Flash memory at, and
below, 20nm (nanometer) is still largely unexplored by researchers,
and with the ever more commonplace existence of Flash in consumer
and enterprise applications there is a need for such gaps in knowledge
to be filled. At the time of writing, there was little published data
or literature on TLC, and more specifically reliability testing, with
a further emphasis on both endurance and retention. This paper
will give an introduction to NAND Flash memory, followed by an
overview of the relevant current research on the reliability of Flash
memory, along with the planned future work which will provide
results to help characterise the reliability of TLC memory.
Abstract: Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.
Abstract: Flash memory has become an important storage device
in many embedded systems because of its high performance, low
power consumption and shock resistance. Multi-level cell (MLC) is
developed as an effective solution for reducing the cost and increasing
the storage density in recent years. However, most of flash file system
cannot handle the error correction sufficiently. To correct more errors
for MLC, we implement Reed-Solomon (RS) code to YAFFS, what is
widely used for flash-based file system. RS code has longer computing
time but the correcting ability is much higher than that of Hamming
code.
Abstract: Cell phone forensics to acquire and analyze data in the
cellular phone is nowadays being used in a national investigation
organization and a private company. In order to collect cellular phone
flash memory data, we have two methods. Firstly, it is a logical
method which acquires files and directories from the file system of the
cell phone flash memory. Secondly, we can get all data from bit-by-bit
copy of entire physical memory using a low level access method. In
this paper, we describe a forensic tool to acquire cell phone flash
memory data using a logical level approach. By our tool, we can get
EFS file system and peek memory data with an arbitrary region from
Korea CDMA cell phone.
Abstract: The flash memory has many advantages such as low power consumption, strong shock resistance, fast I/O and non-volatility. And it is increasingly used in the mobile storage device. The YAFFS, one of the NAND flash file system, is widely used in the embedded device. However, the existing YAFFS takes long time to mount the file system because it scans whole spare areas in all pages of NAND flash memory. In order to solve this problem, we propose a new content-based flash file system using a mounting time reduction technique. The proposed method only scans partial spare areas of some special pages by using content-based block management. The experimental results show that the proposed method reduces the average mounting time by 87.2% comparing with JFFS2 and 69.9% comparing with YAFFS.