The Characterisation of TLC NAND Flash Memory, Leading to a Definable Endurance/Retention Trade-Off
Triple-Level Cell (TLC) NAND Flash memory at, and
below, 20nm (nanometer) is still largely unexplored by researchers,
and with the ever more commonplace existence of Flash in consumer
and enterprise applications there is a need for such gaps in knowledge
to be filled. At the time of writing, there was little published data
or literature on TLC, and more specifically reliability testing, with
a further emphasis on both endurance and retention. This paper
will give an introduction to NAND Flash memory, followed by an
overview of the relevant current research on the reliability of Flash
memory, along with the planned future work which will provide
results to help characterise the reliability of TLC memory.
[1] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash Memory Cells - An
Overview,” Proceedings of the IEEE, vol. 85, no. 8, pp. 1248 –1271,
aug 1997. (Online). Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.
ie/stamp/stamp.jsp?tp=&arnumber=622505
[2] S. Aritome, R. Shirota, G. Hemink, T. Endoh, and F. Masuoka,
“Reliability issues of flash memory cells,” Proceedings of the
IEEE, vol. 81, no. 5, pp. 776 –788, may 1993. (Online).
Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.ie/stamp/stamp.jsp?
tp=&arnumber=220908
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Semiconductor Arrays,” IEEE Std 1005-1998, 1998, endurance: Pg 86,
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[5] C. Compagnoni, C. Miccoli, R. Mottadelli, S. Beltrami, M. Ghidotti,
A. Lacaita, A. Spinelli, and A. Visconti, “Investigation of the
Threshold Voltage Instability after Distributed Cycling in Nanoscale
NAND Flash Memory Arrays,” in Reliability Physics Symposium
(IRPS), 2010 IEEE International, may 2010, pp. 604 –610.
(Online). Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.ie/stamp/
stamp.jsp?tp=&arnumber=5488762
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for Non-Volatile Memories. Springer, 1998, vol. XII. (Online).
Available: http://www.springer.com/engineering/circuits+%26+systems/
book/978-1-4020-8390-7
[7] G. Dong, N. Xie, and T. Zhang, “On the Use of Soft-Decision
Error-Correction Codes in NAND Flash Memory,” Circuits and Systems
I: Regular Papers, IEEE Transactions on, vol. 58, no. 2, pp. 429–439,
Feb 2011. (Online). Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.
ie/stamp/stamp.jsp?tp=&arnumber=5629456
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CMOS,” Santa Clara, CA: Flash Memory Summit, 2012.
(Online). Available: http://www.flashmemorysummit.com/English/
Collaterals/Proceedings/2012/20120822 TE22 Yeo.pdf
[9] J. Wang, T. Courtade, H. Shankar, and R. Wesel, “Soft Information for
LDPC Decoding in Flash: Mutual-Information Optimized Quantization,”
in Global Telecommunications Conference (GLOBECOM 2011), 2011
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org.mislibsrv.lit.ie/stamp/stamp.jsp?tp=&arnumber=6134417
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with Emphasis on Flash, ser. IEEE Press Series on Microelectronic
Systems, J. E. Brewer and M. Gill, Eds. 445 Hoes Lane, Piscataway,
NJ 08854: IEEE Press Series, 2008.
[11] P. Desnoyers, “Empirical Evaluation of NAND Flash Memory
Performance,” SIGOPS Oper. Syst. Rev., vol. 44, no. 1, pp. 50–54, Mar.
2010. (Online). Available: http://doi.acm.org/10.1145/1740390.1740402
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Flash memory manufacturers worldwide from 1st quarter
2010 to 3rd quarter 2015. The Statistics Portal.
(Online). Available:http://www.statista.com/statistics/275886/marketshare-
held-by-leading-nand-flash-memory-manufacturers-worldwide
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ie/stamp/stamp.jsp?tp=&arnumber=1199079
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Distribution in MLC NAND Flash Memory: Characterization, Analysis
and Modeling,” in Design, Automation Test in Europe Conference
Exhibition (DATE), 2013, 2013, pp. 1285–1290. (Online). Available:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=
6513712&queryText%3Dthreshold+voltage+distribution+in+mlc+nand+
flash+memory%3A+characterization%2C+analysis+and+modeling
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pp. 4B.3.1–4B.3.5.
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Memory by Salvaging Bad Blocks,” in Proceedings of the Conference
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CA, USA: EDA Consortium, 2012, pp. 260–263. (Online). Available:
http://dl.acm.org/citation.cfm?id=2492708.2492773
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2592798.2592818
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in Proceedings of SYSTOR 2009: The Israeli Experimental Systems
Conference, ser. SYSTOR ’09. New York, NY, USA: ACM, 2009,
pp. 10:1–10:9. (Online). Available: http://doi.acm.org/10.1145/1534530.
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Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.ie/xpl/articleDetails.
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for Endurance Enhancement and Interference Mitigation
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Electron Devices, IEEE Transactions on, vol. 62, no. 5, pp. 1491–1497,
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[1] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash Memory Cells - An
Overview,” Proceedings of the IEEE, vol. 85, no. 8, pp. 1248 –1271,
aug 1997. (Online). Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.
ie/stamp/stamp.jsp?tp=&arnumber=622505
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“Reliability issues of flash memory cells,” Proceedings of the
IEEE, vol. 81, no. 5, pp. 776 –788, may 1993. (Online).
Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.ie/stamp/stamp.jsp?
tp=&arnumber=220908
[3] IEEE, “IEEE Standard Definitions and Characterization of Floating Gate
Semiconductor Arrays,” IEEE Std 1005-1998, 1998, endurance: Pg 86,
Section 7.
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JESD47H-01, Jedec Solid State Technology Association, Published by
JEDEC Solid State Technology Association 2011 3103 North 10th
Street, Suite 240 South Arlington, VA 22201, APRIL 2011.
[5] C. Compagnoni, C. Miccoli, R. Mottadelli, S. Beltrami, M. Ghidotti,
A. Lacaita, A. Spinelli, and A. Visconti, “Investigation of the
Threshold Voltage Instability after Distributed Cycling in Nanoscale
NAND Flash Memory Arrays,” in Reliability Physics Symposium
(IRPS), 2010 IEEE International, may 2010, pp. 604 –610.
(Online). Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.ie/stamp/
stamp.jsp?tp=&arnumber=5488762
[6] R. Micheloni, A. Marelli, and R. Ravasio, Error Correction Codes
for Non-Volatile Memories. Springer, 1998, vol. XII. (Online).
Available: http://www.springer.com/engineering/circuits+%26+systems/
book/978-1-4020-8390-7
[7] G. Dong, N. Xie, and T. Zhang, “On the Use of Soft-Decision
Error-Correction Codes in NAND Flash Memory,” Circuits and Systems
I: Regular Papers, IEEE Transactions on, vol. 58, no. 2, pp. 429–439,
Feb 2011. (Online). Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.
ie/stamp/stamp.jsp?tp=&arnumber=5629456
[8] E. Yeo, “AN LDPC-Enabled Flash Controller in 40nm
CMOS,” Santa Clara, CA: Flash Memory Summit, 2012.
(Online). Available: http://www.flashmemorysummit.com/English/
Collaterals/Proceedings/2012/20120822 TE22 Yeo.pdf
[9] J. Wang, T. Courtade, H. Shankar, and R. Wesel, “Soft Information for
LDPC Decoding in Flash: Mutual-Information Optimized Quantization,”
in Global Telecommunications Conference (GLOBECOM 2011), 2011
IEEE, Dec 2011, pp. 1–6. (Online). Available: http://0-ieeexplore.ieee.
org.mislibsrv.lit.ie/stamp/stamp.jsp?tp=&arnumber=6134417
[10] S. K. Tewksbury and J. E. Brewer, Nonvolatile Memory Technologies
with Emphasis on Flash, ser. IEEE Press Series on Microelectronic
Systems, J. E. Brewer and M. Gill, Eds. 445 Hoes Lane, Piscataway,
NJ 08854: IEEE Press Series, 2008.
[11] P. Desnoyers, “Empirical Evaluation of NAND Flash Memory
Performance,” SIGOPS Oper. Syst. Rev., vol. 44, no. 1, pp. 50–54, Mar.
2010. (Online). Available: http://doi.acm.org/10.1145/1740390.1740402
[12] Statista. (2015) Global market share held by NAND
Flash memory manufacturers worldwide from 1st quarter
2010 to 3rd quarter 2015. The Statistics Portal.
(Online). Available:http://www.statista.com/statistics/275886/marketshare-
held-by-leading-nand-flash-memory-manufacturers-worldwide
[13] J. H. Yoon, “3D NAND Technology Implications to Enterprise
Storage Applications,” Santa Clara, CA, USA: Flash Memory Summit,
August 2015. (Online). Available: http://www.flashmemorysummit.com/
English/Collaterals/Proceedings/2015/20150811 FM12 Yoon.pdf
[14] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to
Flash Memory,” Proceedings of the IEEE, vol. 91, no. 4, pp. 489 – 502,
april 2003. (Online). Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.
ie/stamp/stamp.jsp?tp=&arnumber=1199079
[15] P. Hasler and T. Lande, “Overview of floating-gate devices, circuits,
and systems,” Circuits and Systems II: Analog and Digital Signal
Processing, IEEE Transactions on, vol. 48, no. 1, pp. 1 –3, jan
2001. (Online). Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.ie/
stamp/stamp.jsp?tp=&arnumber=913180 [16] Y. Cai, E. F. Haratsch, O. Mutlu, and K. Mai, “Threshold Voltage
Distribution in MLC NAND Flash Memory: Characterization, Analysis
and Modeling,” in Design, Automation Test in Europe Conference
Exhibition (DATE), 2013, 2013, pp. 1285–1290. (Online). Available:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=
6513712&queryText%3Dthreshold+voltage+distribution+in+mlc+nand+
flash+memory%3A+characterization%2C+analysis+and+modeling
[17] L. Zuolo, C. Zambelli, R. Micheloni, D. Bertozzi, and P. Olivo,
“Analysis of reliability/performance trade-off in Solid State Drives ,”
in Reliability Physics Symposium, 2014 IEEE International, June 2014,
pp. 4B.3.1–4B.3.5.
[18] C. Wang and W.-F. Wong, “Extending the Lifetime of NAND Flash
Memory by Salvaging Bad Blocks,” in Proceedings of the Conference
on Design, Automation and Test in Europe, ser. DATE ’12. San Jose,
CA, USA: EDA Consortium, 2012, pp. 260–263. (Online). Available:
http://dl.acm.org/citation.cfm?id=2492708.2492773
[19] P. Huang, G. Wu, X. He, and W. Xiao, “An Aggressive Worn-out
Flash Block Management Scheme to Alleviate SSD Performance
Degradation,” in Proceedings of the Ninth European Conference on
Computer Systems, ser. EuroSys ’14. New York, NY, USA: ACM,
2014, pp. 22:1–22:14. (Online). Available: http://doi.acm.org/10.1145/
2592798.2592818
[20] X.-Y. Hu, E. Eleftheriou, R. Haas, I. Iliadis, and R. Pletka,
“Write Amplification Analysis in Flash-based Solid State Drives,”
in Proceedings of SYSTOR 2009: The Israeli Experimental Systems
Conference, ser. SYSTOR ’09. New York, NY, USA: ACM, 2009,
pp. 10:1–10:9. (Online). Available: http://doi.acm.org/10.1145/1534530.
1534544
[21] R. Agarwal and M. Marrow, “A closed-form expression for
write amplification in NAND Flash,” in GLOBECOM Workshops
(GC Wkshps), 2010 IEEE, Dec 2010, pp. 1846–1850. (Online).
Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.ie/stamp/stamp.jsp?
tp=&arnumber=5700261
[22] J. Guo, Z. Chen, D. Wang, Z. Shao, and Y. Chen, “DPA: A data
pattern aware error prevention technique for NAND flash lifetime
extension,” in Design Automation Conference (ASP-DAC), 2014
19th Asia and South Pacific, Jan 2014, pp. 592–597. (Online).
Available: http://0-ieeexplore.ieee.org.mislibsrv.lit.ie/xpl/articleDetails.
jsp?arnumber=6742955&queryText=DPA%3A+A+data+pattern+aware+
error+prevention+technique+for+NAND+flash+lifetime+extension&
newsearch=true&searchField=Search All
[23] J. Cha and S. Kang, “Data Randomization Scheme
for Endurance Enhancement and Interference Mitigation
of Multilevel Flash Memory Devices,” ETRI Journal,
vol. 35, no. 1, pp. 166–169, February 2013. (Online).
Available: http://dx.doi.org/10.4218/etrij.13.0212.0273http://etrij.etri.re.
kr/etrij/journal/article/article.do?volume=35&issue=1&page=166
[24] G. Paolucci, C. Compagnoni, A. Spinelli, A. Lacaita, and A. Goda,
“Fitting Cells Into a Narrow VT Interval: Physical Constraints Along
the Lifetime of an Extremely Scaled NAND Flash Memory Array,”
Electron Devices, IEEE Transactions on, vol. 62, no. 5, pp. 1491–1497,
May 2015. (Online). Available: http://ieeexplore.ieee.org/xpl/login.jsp?
tp=&arnumber=7089352&url=http%3A%2F%2Fieeexplore.ieee.org%
2Fxpls%2Fabs all.jsp%3Farnumber%3D7089352
[25] V. Mohan, S. Sankar, and S. Gurumurthi, “reFresh SSDs: Enabling
High Endurance, Low Cost Flash in Datacenters,” University of
Virginia, Department of Computer Science University of Virginia
Charlottesville, VA 22904, Tech. Rep., May 2012. (Online). Available:
http://www.cs.virginia.edu/∼vm9u/files/RefreshSSDs.pdf
[26] Y. Cai, G. Yalcin, O. Mutlu, E. Haratsch, A. Cristal,
O. Unsal, and K. Mai, “Flash correct-and-refresh: Retention-aware
error management for increased flash memory lifetime,” in
Computer Design (ICCD), 2012 IEEE 30th International
Conference on, 2012, pp. 94–101. (Online). Available:
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=
6378623&queryText%3Dflash+correct-and-refresh%3A+retentionaware+
error+management+for+increased+flash+memory+lifetime
[27] Y. Cai, G. Yalcin, O. Mutlu, E. Haratsch, A. Cristal, O. Unsal,
and K. Mai, “Error Analysis and Retention-Aware Error
Management for NAND Flash Memory,” Intel, Technology Journal
Paper 8, Volume 17, Issue 1, 2013. (Online). Available:https:
//noggin.intel.com/system/files/article/paper-8-error-analysis-andretention-
aware-error-management-for-nand-flash-memory.pdf
[28] C.-L. Y. Ren-Shuo Liu and W. Wu, “Optimizing NAND Flash-Based
SSDs via Retention Relaxation,” 10th USENIX Conference on File
and Storage Technologies. San Jose, CA: USENIX FAST, February
15th 2012. (Online). Available: http://static.usenix.org/events/fast/tech/
full papers/Liu.pdf
[29] Y. Pan, G. Dong, Q. Wu, and T. Zhang, “Quasi-nonvolatile SSD:
Trading flash memory nonvolatility to improve storage system
performance for enterprise applications,” in High Performance
Computer Architecture (HPCA), 2012 IEEE 18th International
Symposium on, Feb 2012, pp. 1–10. (Online). Available: http:
//0-ieeexplore.ieee.org.mislibsrv.lit.ie/xpl/articleDetails.jsp?arnumber=
6168954&queryText=Quasi-nonvolatile+ssd%3A+Trading+flash+
memory+nonvolatility+to+improve+storage+system+performance+for+
enterprise+applications&newsearch=true&searchField=Search All
[30] Y. Luo, Y. Cai, S. Ghose, J. Choi, O. Mutlu, “WARM: Improving
NAND flash memory lifetime with write-hotness aware retention
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@article{"International Journal of Information, Control and Computer Sciences:72583", author = "Sorcha Bennett and Joe Sullivan", title = "The Characterisation of TLC NAND Flash Memory, Leading to a Definable Endurance/Retention Trade-Off", abstract = "Triple-Level Cell (TLC) NAND Flash memory at, and
below, 20nm (nanometer) is still largely unexplored by researchers,
and with the ever more commonplace existence of Flash in consumer
and enterprise applications there is a need for such gaps in knowledge
to be filled. At the time of writing, there was little published data
or literature on TLC, and more specifically reliability testing, with
a further emphasis on both endurance and retention. This paper
will give an introduction to NAND Flash memory, followed by an
overview of the relevant current research on the reliability of Flash
memory, along with the planned future work which will provide
results to help characterise the reliability of TLC memory.", keywords = "TLC NAND flash memory, reliability, endurance,
retention, trade-off, raw flash, patterns.", volume = "10", number = "4", pages = "716-8", }
