Abstract: This paper presents the findings of successful implementation of Business Process Reengineering (BPR) of cement dispatch activities in a cement manufacturing plant located in India. Simulation model was developed for the purpose of identifying and analyzing the areas for improvement. The company was facing a problem of low throughput rate and subsequent forced stoppages of the plant leading to a high production loss of 15000MT per month. It was found from the study that the present systems and procedures related to the in-plant logistics plant required significant changes. The major recommendations included process improvement at the entry gate, reducing the cycle time at the security gate and installation of an additional weigh bridge. This paper demonstrates how BPR can be implemented for improving the in-plant logistics process. Various recommendations helped the plant to increase its throughput by 14%.
Abstract: An efficient remanufacturing network lead to an
efficient design of sustainable manufacturing enterprise. In
remanufacturing network, products are collected from the customer
zone, disassembled and remanufactured at a suitable remanufacturing
facility. In this respect, another issue to consider is how the returned
product to be remanufactured, in other words, what is the best layout
for such facility. In order to achieve a sustainable manufacturing
system, Cellular Manufacturing System (CMS) designs are highly
recommended, CMSs combine high throughput rates of line layouts
with the flexibility offered by functional layouts (job shop).
Introducing the CMS while designing a remanufacturing network will
benefit the utilization of such a network. This paper presents and
analyzes a comprehensive mathematical model for the design of
Dynamic Cellular Remanufacturing Systems (DCRSs). In this paper,
the proposed model is the first one to date that considers CMS and
remanufacturing system simultaneously. The proposed DCRS model
considers several manufacturing attributes such as multi period
production planning, dynamic system reconfiguration, duplicate
machines, machine capacity, available time for workers, worker
assignments, and machine procurement, where the demand is totally
satisfied from a returned product. A numerical example is presented
to illustrate the proposed model.
Abstract: Assembly line balancing problem is aimed to divide
the tasks among the stations in assembly lines and optimize some
objectives. In assembly lines the workload on stations is different
from each other due to different tasks times and the difference in
workloads between stations can cause blockage or starvation in some
stations in assembly lines. Buffers are used to store the semi-finished
parts between the stations and can help to smooth the assembly
production. The assembly line balancing and buffer sizing problem
can affect the throughput of the assembly lines. Assembly line
balancing and buffer sizing problems have been studied separately in
literature and due to their collective contribution in throughput rate of
assembly lines, balancing and buffer sizing problem are desired to
study simultaneously and therefore they are considered concurrently
in current research. Current research is aimed to maximize
throughput, minimize total size of buffers in assembly line and
minimize workload variations in assembly line simultaneously. A
multi objective optimization objective is designed which can give
better Pareto solutions from the Pareto front and a simple example
problem is solved for assembly line balancing and buffer sizing
simultaneously. Current research is significant for assembly line
balancing research and it can be significant to introduce optimization
approaches which can optimize current multi objective problem in
future.
Abstract: The purpose of this work is examining the multiproduct
multi-stage in a battery production line. To improve the
performances of an assembly production line by determine the
efficiency of each workstation. Data collected from every
workstation. The data are throughput rate, number of operator, and
number of parts that arrive and leaves during part processing. Data
for the number of parts that arrives and leaves are collected at least at
the amount of ten samples to make the data is possible to be analyzed
by Chi-Squared Goodness Test and queuing theory. Measures of this
model served as the comparison with the standard data available in
the company. Validation of the task time value resulted by comparing
it with the task time value based on the company database. Some
performance factors for the multi-product multi-stage in a battery
production line in this work are shown.
The efficiency in each workstation was also shown. Total
production time to produce each part can be determined by adding
the total task time in each workstation. To reduce the queuing time
and increase the efficiency based on the analysis any probably
improvement should be done. One probably action is by increasing
the number of operators how manually operate this workstation.
Abstract: The purpose of this paper is to simulate the production process of a metal stamping industry and to evaluate the utilization of the production line by using ARENA simulation software. The process time and the standard time for each process of the production line is obtained from data given by the company management. Other data are collected through direct observation of the line. There are three work stations performing ten different types of processes in order to produce a single product type. Arena simulation model is then developed based on the collected data. Verification and validation are done to the Arena model, and finally the result of Arena simulation can be analyzed. It is found that utilization at each workstation will increase if batch size is increased although throughput rate remains/is kept constant. This study is very useful for the company because the company needs to improve the efficiency and utilization of its production lines.
Abstract: In this paper, we propose a fully-utilized, block-based 2D DWT (discrete wavelet transform) architecture, which consists of four 1D DWT filters with two-channel QMF lattice structure. The proposed architecture requires about 2MN-3N registers to save the intermediate results for higher level decomposition, where M and N stand for the filter length and the row width of the image respectively. Furthermore, the proposed 2D DWT processes in horizontal and vertical directions simultaneously without an idle period, so that it computes the DWT for an N×N image in a period of N2(1-2-2J)/3. Compared to the existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rates. To mitigate the long critical path delay due to the cascaded lattices, we can apply the pipeline technique with four stages, while retaining 100% of hardware utilization. The proposed architecture can be applied in real-time video signal processing.
Abstract: The dynamic spectrum allocation solutions such as
cognitive radio networks have been proposed as a key technology to
exploit the frequency segments that are spectrally underutilized.
Cognitive radio users work as secondary users who need to
constantly and rapidly sense the presence of primary users or
licensees to utilize their frequency bands if they are inactive. Short
sensing cycles should be run by the secondary users to achieve
higher throughput rates as well as to provide low level of interference
to the primary users by immediately vacating their channels once
they have been detected. In this paper, the throughput-sensing time
relationship in local and cooperative spectrum sensing has been
investigated under two distinct scenarios, namely, constant primary
user protection (CPUP) and constant secondary user spectrum
usability (CSUSU) scenarios. The simulation results show that the
design of sensing slot duration is very critical and depends on the
number of cooperating users under CPUP scenario whereas under
CSUSU, cooperating more users has no effect if the sensing time
used exceeds 5% of the total frame duration.
Abstract: An effective approach for realizing the binary tree structure, representing a combinational logic functionality with enhanced throughput, is discussed in this paper. The optimization in maximum operating frequency was achieved through delay minimization, which in turn was possible by means of reducing the depth of the binary network. The proposed synthesis methodology has been validated by experimentation with FPGA as the target technology. Though our proposal is technology independent, yet the heuristic enables better optimization in throughput even after technology mapping for such Boolean functionality; whose reduced CNF form is associated with a lesser literal cost than its reduced DNF form at the Boolean equation level. For cases otherwise, our method converges to similar results as that of [12]. The practical results obtained for a variety of case studies demonstrate an improvement in the maximum throughput rate for Spartan IIE (XC2S50E-7FT256) and Spartan 3 (XC3S50-4PQ144) FPGA logic families by 10.49% and 13.68% respectively. With respect to the LUTs and IOBUFs required for physical implementation of the requisite non-regenerative logic functionality, the proposed method enabled savings to the tune of 44.35% and 44.67% respectively, over the existing efficient method available in literature [12].
Abstract: In a state-of-the-art industrial production line of
photovoltaic products the handling and automation processes are of
particular importance and implication. While processing a fully
functional crystalline solar cell an as-cut photovoltaic wafer is subject
to numerous repeated handling steps. With respect to stronger
requirements in productivity and decreasing rejections due to defects
the mechanical stress on the thin wafers has to be reduced to a
minimum as the fragility increases by decreasing wafer thicknesses.
In relation to the increasing wafer fragility, researches at the
Fraunhofer Institutes IPA and CSP showed a negative correlation
between multiple handling processes and the wafer integrity. Recent
work therefore focused on the analysis and optimization of the dry
wafer stack separation process with compressed air. The achievement
of a wafer sensitive process capability and a high production
throughput rate is the basic motivation in this research.